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1024LI-42TE13 参数 Datasheet PDF下载

1024LI-42TE13图片预览
型号: 1024LI-42TE13
PDF下载: 下载PDF文件 查看货源
内容描述: [Power Supply Support Circuit, Fixed, 1 Channel, CMOS, PDIP8, PLASTIC, DIP-8]
分类和应用: 光电二极管
文件页数/大小: 17 页 / 107 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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Preliminary Information  
CAPACITANCE  
CAT1024, CAT1025  
T = 25°C, f = 1.0 MHz, V  
A
= 5V  
CC  
Symbol Test  
Test Conditions  
VOUT = 0V  
Max  
8
Units  
(1)  
COUT  
Output Capacitance  
Input Capacitance  
pF  
pF  
(1)  
CIN  
VIN = 0V  
6
A.C. CHARACTERISTICS  
VCC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.  
Memory Read & Write Cycle2  
Symbol  
Parameter  
Min  
Max  
Units  
fSCL  
Clock Frequency  
400  
kHz  
Input Filter Spike  
Suppression (SDA, SCL)  
tSP  
100  
ns  
tLOW  
tHIGH  
Clock Low Period  
Clock High Period  
1.3  
0.6  
µs  
µs  
ns  
ns  
µs  
1
tR  
SDA and SCL Rise Time  
SDA and SCL Fall Time  
Start Condition Hold Time  
300  
300  
1
tF  
tHD;STA  
tSU;STA  
0.6  
0.6  
Start Condition Setup Time  
(for a Repeated Start)  
µs  
tHD;DAT  
tSU;DAT  
tSU;STO  
tAA  
Data Input Hold Time  
Data Input Setup Time  
Stop Condition Setup Time  
SCL Low to Data Out Valid  
Data Out Hold Time  
0
ns  
ns  
µs  
ns  
ns  
100  
0.6  
900  
tDH  
50  
Time the Bus must be Free Before a  
New Transmission Can Start  
1
tBUF  
1.3  
µs  
3
tWC  
Write Cycle Time (Byte or Page)  
5
ms  
Notes:  
1. This parameter is characterized initially and after a design or process change that affects  
the parameter. Not 100% tested.  
2. Test Conditions according to “AC Test Conditions” table.  
3. The write cycle time is the time from a valid stop condition of a write sequence to the end of  
the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled,  
SDA is allowed to remain high and the device does not respond to its slave address.  
Doc No. 3008, Rev. G  
5
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