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1024LI-42TE13 参数 Datasheet PDF下载

1024LI-42TE13图片预览
型号: 1024LI-42TE13
PDF下载: 下载PDF文件 查看货源
内容描述: [Power Supply Support Circuit, Fixed, 1 Channel, CMOS, PDIP8, PLASTIC, DIP-8]
分类和应用: 光电二极管
文件页数/大小: 17 页 / 107 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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Preliminary Information  
CAT1024, CAT1025  
EMBEDDED EEPROM OPERATION  
SDA when SCL is HIGH. The CAT1024/25 monitors the  
SDA and SCL lines and will not respond until this  
condition is met.  
The CAT1024 and CAT1025 feature a 2kbit embedded  
serial EEPROM that supports the I2C Bus data  
transmission protocol. This Inter-Integrated Circuit Bus  
protocol defines any device that sends data to the bus to  
be a transmitter and any device receiving data to be a  
receiver. The transfer is controlled by the Master device  
which generates the serial clock and all START and  
STOPconditionsforbusaccess.BoththeMasterdevice  
and Slave device can operate as either transmitter or  
receiver, but the Master device controls which mode is  
activated.  
STOP Condition  
A LOW to HIGH transition of SDA when SCL is HIGH  
determinestheSTOPcondition.Alloperationsmustend  
with a STOP condition.  
DEVICE ADDRESSING  
The Master begins a transmission by sending a START  
condition.TheMastersendstheaddressoftheparticular  
slave device it is requesting. The four most significant  
bitsofthe8-bitslaveaddressareprogrammableinmetal  
and the default is 1010.  
I2C Bus Protocol  
The features of the I2C bus protocol are defined as  
follows:  
(1) Data transfer may be initiated only when the bus is  
not busy.  
The last bit of the slave address specifies whether a  
ReadorWriteoperationistobeperformed.Whenthisbit  
is set to 1, a Read operation is selected, and when set  
to 0, a Write operation is selected.  
(2) During a data transfer, the data line must remain  
stable whenever the clock line is high. Any changes in  
thedatalinewhiletheclocklineishighwillbeinterpreted  
as a START or STOP condition.  
After the Master sends a START condition and the slave  
address byte, the CAT1024/25 monitors the bus and  
responds with an acknowledge (on the SDA line) when  
its address matches the transmitted slave address. The  
CAT1024/25 then performs a Read or Write operation  
depending on the R/W bit.  
START Condition  
The START Condition precedes all commands to the  
device, and is defined as a HIGH to LOW transition of  
Figure 3. Bus Timing  
t
t
t
F
HIGH  
R
t
t
LOW  
LOW  
SCL  
t
t
HD:DAT  
SU:STA  
t
t
t
t
HD:STA  
SU:DAT  
SU:STO  
SDA IN  
BUF  
t
t
DH  
AA  
SDA OUT  
Figure 4. Write Cycle Timing  
SCL  
SDA  
8TH BIT  
BYTE n  
ACK  
t
WR  
STOP  
CONDITION  
START  
CONDITION  
ADDRESS  
Doc No. 3008, Rev. G  
9
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