CAT1024, CAT1025
Preliminary Information
ACKNOWLEDGE
WRITE OPERATIONS
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
Byte Write
In the Byte Write mode, the Master device sends the
STARTconditionandtheslaveaddressinformation(with
theR/Wbitsettozero)totheSlavedevice.AftertheSlave
generates an acknowledge, the Master sends a 8-bit
address that is to be written into the address pointers of
thedevice. Afterreceivinganotheracknowledgefromthe
Slave, the Master device transmits the data to be written
into the addressed memory location. The CAT1024/25
acknowledges once more and the Master generates the
STOP condition. At this time, the device begins an
internalprogrammingcycletonon-volatilememory.While
the cycle is in progress, the device will not respond to any
request from the Master device.
The CAT1024/25 responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress.Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
WhentheCAT1024/25beginsaREADmodeittransmits
8 bits of data, releases the SDA line and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT1024/25 will continue to transmit
data.IfnoacknowledgeissentbytheMaster,thedevice
terminates data transmission and waits for a STOP
condition.
Figure 5. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 6. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 7. Slave Address Bits
Default Configuration
1
0
1
0
0
0
0
R/W
CAT
Doc. No. 3008, Rev. G
10
CATALYST [ CATALYST SEMICONDUCTOR ]
