PRODUCT SPECIFICATION
TMC22x5yA
VINDO Operation
Video Measurement
The VINDO circuit uses the line idents on LID , and the
4-0
The TMC22x5yA supports a comprehensive set of video
measurement techniques to aid the user in setting up the
gain, phase, etc. of the decoder and in tracking down system
errors.
blanking signals to control the comb filter output and the
blanking of the YUV data in the output matrix during the
vertical blanking period.
The vertical window VINDO starts on the first line after the
Pixel Grab
last equalizing pulse, at LID = 02. The VINDO stays
4-0
The pixel grab allows the user to grab one pixel every line,
or one pixel out of the four field sequence in NTSC or the 8
field sequence in PAL, under software control. The SET pin
HIGH from this line until the VINDO count = VINDO , or
4-0
the VBLK signal goes HIGH, at which time the VINDO goes
LOW. While the VINDO is HIGH the decoder operation is
controlled by VDIV, and during the time the VINDO and
VBLK are LOW the decoder operation is controlled by
VDOV.
can also be used to produce the pixel grab pulse if SET
110 and PGEXT is set HIGH.
=
2-0
The 10 bit G/Y, B/U, R/V outputs are stored in one set of
four 8 bit registers in the FORMAT block, while the 10 bit
Table 22. PAL VINDO operation
luma and mixed sync data and the 10 bit demodulated U and
V color difference signals are stored in a set of five 8 bit
registers in the GRAB circuit block. The pixel grab signal,
PIXEL, whether internally or externally generated, is inter-
nally delayed to ensure that the all the grabbed data are from
the same pixel relative to the line sync pulse. The PIXEL
signal is equal to PGRAB or the logical AND of PGRAB
with FGRAB and LGRAB, and is controlled by the LPGEN,
PGEN, and PGEXT register bits.
LID
4-0
VINDO VDIV VDOV
Y
C
00 - 01
02 - 0A
02 - 0A
02 - 0A
02 - 0A
0B - 17
x
1
1
0
0
x
x
0
1
x
x
x
x
x
x
0
1
x
normal normal
simple simple
flat
black
black
black
simple black
normal normal
The luma and mixed sync signals are multiplexed on the
YMS data bus and the U and V signals are multiplexed on
the UV data bus, at the PXCK clock rate. The pixel grab
signal accommodates for this when grabbing these
components.
NTSC VINDO operation
LID VINDO VDIV VDOV
Y
C
4-0
00 - 02
03 - 06
03 - 06
03 - 06
03 - 06
07 - 17
x
1
1
0
0
x
x
0
1
x
x
x
x
x
x
0
1
x
normal normal
simple simple
An example of the pixel grab feature, is grabbing a pixel in
the center of the burst period allowing the user to check the
burst height by reading the magnitude of the demodulated U
and V components. This allows the user to compensate for
any chrominance gain errors in the output matrix.
flat
black
black
black
black
simple
normal normal
Y
Y Data
C Data
YMS
Luma
Video A
Video B
dT
Proc
MS
Luma and
Chroma
Separation
G/Y
U
V
Output
LPF
Output
Matrix
Chroma
Demodulation
Formatter
and Buffer
UV
B/U
R/V
LPF
U Data
Grab
register 3A/3C
V Data
Grab
G/Y
Grab
register 3B/3C
register 34/37
Y Data
Grab
B/U
Grab
register 38/3C
register 35/37
MS Data
Grab
RV
Grab
register 39/3C
register 36/37
65-22x5y-72
Pixel
dT
Figure 32. Pixel Grab Locations
REV. 1.0.0 2/4/03
65
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
