欢迎访问ic37.com |
会员登录 免费注册
发布采购

TMC22153AKHC 参数 Datasheet PDF下载

TMC22153AKHC图片预览
型号: TMC22153AKHC
PDF下载: 下载PDF文件 查看货源
内容描述: 多标准数字视频解码器三线自适应梳状解码器系列, 8和10位 [Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit]
分类和应用: 解码器
文件页数/大小: 84 页 / 515 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
 浏览型号TMC22153AKHC的Datasheet PDF文件第64页浏览型号TMC22153AKHC的Datasheet PDF文件第65页浏览型号TMC22153AKHC的Datasheet PDF文件第66页浏览型号TMC22153AKHC的Datasheet PDF文件第67页浏览型号TMC22153AKHC的Datasheet PDF文件第69页浏览型号TMC22153AKHC的Datasheet PDF文件第70页浏览型号TMC22153AKHC的Datasheet PDF文件第71页浏览型号TMC22153AKHC的Datasheet PDF文件第72页  
TMC22x5yA  
PRODUCT SPECIFICATION  
t
t
PWHCS  
PWLCS  
CS  
R/W  
ADR  
t
t
HA  
SA  
t
t
SD  
HD  
D
7-0  
65-22x5y-16  
Figure 33. Microprocessor Parallel Port Write Timing  
t
t
PWHCS  
PWLCS  
CS  
R/W  
ADR  
t
t
HA  
SA  
t
t
HOM  
DOM  
D
7-0  
65-22x5y-17  
t
DOZ  
Figure 34. Microprocessor Parallel Port Read Timing  
There are six components to serial bus operation:  
Serial Control Port (R-Bus)  
In addition to the 12-wire parallel port, a 2-wire serial  
control interface is provided, and active when SER is LOW.  
Either port alone can control the entire chip. Up to eight  
TMC22x5yA devices may be connected to the 2-wire serial  
interface with each device having a unique address.  
• Start signal  
• Slave address byte  
• Block Pointer  
• Base register address byte  
• Data byte to read or write  
• Stop signal  
The 2-wire interface comprises a clock (SCL) and a bi-direc-  
tional data (SDA) pin. The Decoder acts as a slave for receiv-  
ing and transmitting data over the serial interface. When the  
serial interface is not active, the logic levels on SCL and  
SDA are pulled HIGH by external pull-up resistors.  
When the serial interface is inactive (SCL and SDA are  
HIGH) communications are initiated by sending a start sig-  
nal. The start signal is a HIGH-to-LOW transition on SDA  
while SCL is HIGH. This signal alerts all slaved devices that  
a data transfer sequence is coming.  
Data received or transmitted on the SDA line must be stable  
for the duration of the positive-going SCL pulse. Data on  
SDA must change only when SCL is LOW. If SDA changes  
state while SCL is HIGH, the serial interface interprets that  
action as a start or stop sequence.  
The first eight bits of data transferred after a start signal com-  
prise a seven bit slave address (the first seven bits) and a sin-  
gle R/W bit (the eighth bit). The R/W bit indicates the  
direction of data transfer, read from or write to the slave  
device. If the transmitted slave address matches the address  
of the device (set by the state of the SA input pins in Table  
2-0  
20), the TMC22x5yA acknowledges by bringing SDA LOW  
on the 9th SCL pulse. If the addresses do not match, the  
TMC22x5yA does not acknowledge.  
68  
REV. 1.0.0 2/4/03  
 复制成功!