PRODUCT SPECIFICATION
TMC22091/TMC22191
PXCK
PDC
PD
P
P
P
P
P
P
P
P
P
P
1
2
3
4
19
20
21
22
23
24
COMPOSITE
OUTPUT
P
PI
P
PI
P
2 3
1
1
2
POST-FILTER
OUTPUT
24358A
Figure 17. External Pixel Data Control
Pixels produced by the encoder appear at the analog outputs
(COMPOSITE, LUMA, CHROMA) 40 clocks after they are
registered into the PD port. Note that the pixels enter at one-
half the PXCK rate. The encoded signal passes through
interpolation filters which generate intermediate output val-
ues, improving the output frequency response and greatly
simplifying the external reconstruction filter. The interpo-
lated pixels are designated PI in the diagram.
Internal Pixel Data Control
When programmed as an output, PDC goes HIGH four
PXCK periods prior to the end of CBP (as programmed in
the horizontal timing registers) which is also four PXCK
cycles prior to required input of the first pixel of a line.
PXCK
PDC
t
DO
P
P
P
P
P
P
P
P
P
P
24
PD
1
2
3
4
19
20
21
22
23
COMPOSITE
OUTPUT
P
PI
P
PI
P
2 3
1
1
2
POST-FILTER
OUTPUT
24357A
Figure 18. Internal Pixel Data Control
39
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
