PRODUCT SPECIFICATION
TMC22091/TMC22191
Microprocessor Interface
The microprocessor interface comprises 13-lines. Two
address bits provide four addresses for device programming
and CLUT/register management. Address bit 0 selects
between control registers and CLUT memory. Address bit 1
selects between reading/writing the register addresses and
reading/writing register or CLUT data.
When writing, the address is presented along with a LOW on
the R/W pin during the falling edge of CS. Eight bits of data
are presented on D during the subsequent rising edge of
7-0
CS.
24388A
One additional falling edge of CS is needed to move input
data to the assigned working registers.
Figure 7. Modulated Ramp Waveform
t
t
PWHCS
PWLCS
CS
t
t
HA
SA
R/W
A -A
1
0
0
t
t
HD
SD
D -D
7
24323A
Figure 10. Microprocessor Port – Write Timing
t
t
PWHCS
PWLCS
CS
t
t
HA
SA
R/W
A -A
1
0
0
t
t
HOM
DOM
D -D
7
24324A
t
DOZ
Figure 11. Microprocessor Port – Read Timing
35
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