TMC22091/TMC22191
PRODUCT SPECIFICATION
PXCK
VHSYNC
VVSYNC
1
1
for field 1
COMPOSITE
OUTPUT
50% Sync Amplitude
Figure 15. Slave Mode Timing
24355A
PXCK
GHSYNC
VHSYNC
COMPOSITE
OUTPUT
24356A
50% Sync Amplitude
Figure 16. Genlocked Mode Timing
The position (number of PCK cycles) of the rising edge of
PDC relative to the falling edge of VHSYNC can be found
by summing SY, BU, BR, and CBP. See Figure 17.
Genlocked Mode
In Genlocked mode, the encoder receives sync signals over
the GHSYNC and GVSYNC inputs, and provides VHSYNC
and VVSYNC to the host. The 50% sync amplitude point
occurs 50 PXCK clocks after GHSYNC goes LOW, while
VHSYNC is produced at clock 13. If GHSYNC is late, the
front porch is lengthened, if is is early, front porch is
shortened. See Figure 16, Genlock Mode Timing.
External Pixel Data Control
When used as an input, PDC goes HIGH four PXCK cycles
before the first valid pixel of a line is presented to the PD
input port. If this signal is late (with respect to the horizontal
blanking interval programmed in the timing control regis-
ters), the Color Back Porch (CBP) will be extended. If it is
early, incoming pixel data will be ignored until the end of the
CBP.
Pixel Data Control
The Pixel Data Control (PDC) signal determines the active
picture area. It may be an input or an output, as determined
by the Interface Control Register bit 1.
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