PRODUCT SPECIFICATION
TMC22091/TMC22191
t
t
PWLPX
PWHPX
2N+1
2N+2
2N+3
PXCK
t
SP
t
PWLVH
VHSYNC
(GHSYNC)
PCK
LDV
t
t
PWHLDV
XL
t
PWLLDV
t
t
HP
SP
PD
KEY
24340A
Figure 13. Slave Mode PD Port Interface Timing (Genlock Mode)
0
1
2
3
4
16 17 18 19 20 21
51 52 53 54 55 56 57 58 59 60
PXCK
RESET
VHSYNC
COMPOSITE
OUTPUT
50% Sync Amplitude
24353A
Figure 14. Master Mode Timing
Master Mode
Slave Mode
In Master mode, initial timing is determined from the
RESET input, and subsequent cycles result from pro-
grammed values in the Timing Control Registers. The Hori-
zontal Sync output, VHSYNC, goes LOW 18 PXCK clock
cycles after the device is reset. The 50% point of the falling
edge of sync LOW on line 4 of field 1 (NTSC) or line 1 of
field 1 (PAL) occurs at the COMPOSITE and LUMA out-
puts 56 clocks after reset, or 38 clocks after VHSYNC. See
Figure 14, Master Mode Timing.
In Slave mode, the 50% point of the falling edge of sync
occurs 46 PXCK clocks after the falling edge of VHSYNC,
which is an input signal to the TMC22x91. This must be pro-
vided by the host to begin every line. If it is early, the line
will be started early, maintaining the 52 clock delay to out-
put. If it comes late, the front porch portion of the output
waveform will be extended as necessary. See Figure 15,
Slave Mode Timing.
37
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