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SLES100 − DECEMBER 2003
OS[1:0]: Delta-Sigma Oversampling Rate Selection
These bits are available for read and write.
Default value: 00
OS[1:0]
00
Operation Speed Select
64 times f (default)
S
01
32 times f
S
10
128 times f
Reserved
S
11
The OS bits are used to change the oversampling rate of delta-sigma modulation. Use of this function enables the
designer to stabilize the conditions at the post low-pass filter for different sampling rates. As an application example,
programming to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, and 32 times in 192-kHz operation
allows the use of only a single type (cutoff frequency) of post low-pass filter. The 128 f oversampling rate is not
S
available at sampling rates above 100 kHz. If the 128-f oversampling rate is selected, a system clock of more than
S
256 f is required.
S
In DSD mode, these bits are used to select the speed of the bit clock for DSD data coming into the analog FIR filter.
B15 B14 B13 B12 B11 B10
Register 21 R/W
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
1
0
1
0
1
RSV
RSV
RSV
RSV
RSV
DZ1
DZ0 PCMZ
R/W: Read/Write Mode Select
When R/W = 0, a write operation is performed.
When R/W = 1, a read operation is performed.
Default value: 0
DZ[1:0]: DSD Zero Output Enable
These bits are available for read and write.
Default value: 00
DZ[1:0]
00
Zero Output Enable
Disabled (default)
Even pattern detect
96h pattern detect
01
1x
The DZ bits are used to enable or disable the output zero flags, and to select the zero pattern in the DSD mode.
PCMZ: PCM Zero Output Enable
These bits are available for read and write.
Default value: 1
PCMZ = 0
PCMZ = 1
PCM zero output disabled
PCM zero output enabled (default)
The PCMZ bit is used to enable or disable the output zero flags in the PCM mode and the external DF mode.
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 22
R
0
0
1
0
1
1
0
RSV
RSV
RSV
RSV
RSV
RSV ZFGR ZFGL
R: Read Mode Select
Value is always 1, specifying the readback mode.
31