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PCM1796 参数 Datasheet PDF下载

PCM1796图片预览
型号: PCM1796
PDF下载: 下载PDF文件 查看货源
内容描述: 24位192 kHz的采样高级分段音频立体声数字模拟转换器 [24BIT 192 KHZ SAMPLING ADVANCED SEGMENT AUDIO STEREO DIGITAL TO ANALOG CONVERTER]
分类和应用: 转换器
文件页数/大小: 57 页 / 508 K
品牌: BB [ BURR-BROWN CORPORATION ]
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ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ  
www.ti.com  
SLES100 − DECEMBER 2003  
AUDIO DATA INTERFACE  
Audio Serial Interface  
The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the  
serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio  
interface. Serial data is clocked into the PCM1796 on the rising edge of BCK. LRCK is the serial audio left/right word  
clock.  
The PCM1796 requires the synchronization of LRCK and system clock, but does not need a specific phase relation  
between LRCK and system clock.  
If the relationship between LRCK and system clock changes more than 6 BCK, internal operation is initialized within  
1/f and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock  
S
is completed.  
PCM Audio Data Formats and Timing  
2
The PCM1796 supports industry-standard audio data formats, including standard right-justified, I S, and  
left-justified. The data formats are shown in Figure 27. Data formats are selected using the format bits, FMT[2:0],  
2
in control register 18. The default data format is 24-bit I S. All formats require binary 2s complement, MSB-first audio  
data. Figure 26 shows a detailed timing diagram for the serial audio interface.  
1.4 V  
1.4 V  
1.4 V  
LRCK  
BCK  
t
t
(BCL)  
t
(BCH)  
(LB)  
t
t
(BCY)  
(BL)  
DATA  
t
t
(DS)  
(DH)  
PARAMETERS  
MIN MAX UNITS  
t
t
t
t
t
t
t
BCK pulse cycle time  
BCK pulse duration, LOW  
BCK pulse duration, HIGH  
BCK rising edge to LRCK edge  
LRCK edge to BCK rising edge  
DATA setup time  
70  
30  
30  
10  
10  
10  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(BCY)  
(BCL)  
(BCH)  
(BL)  
(LB)  
(DS)  
DATA hold time  
(DH)  
LRCK clock data  
50% 2 bit clocks  
Figure 26. Timing of Audio Interface  
16  
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