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SLES100 − DECEMBER 2003
SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
The PCM1796 requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input (pin 7). The PCM1796 has a system clock detection circuit
that automatically senses the frequency at which the system clock is operating. Table 1 shows examples of system
clock frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma modulator is selected
as 128 f , the system clock frequency is required to be over 256 f .
S
S
Figure 23 shows the timing requirements for the system clock input. For optimal performance, it is important to use
a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock generators
is an excellent choice for providing the PCM1796 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SYSTEM CLOCK FREQUENCY (f
) (MHz)
SCK
SAMPLING FREQUENCY
128 f
192 f
256 f
384 f
512 f
768 f
S
S
S
S
S
S
(1)
(1)
32 kHz
44.1 kHz
48 kHz
4.096
6.144
8.192
11.2896
12.288
24.576
12.288
16.9344
18.432
36.864
16.384
24.576
33.8688
36.864
(1)
5.6488
8.4672
9.216
22.5792
24.576
(1)
6.144
(1)
49.152
(1)
73.728
96 kHz
12.288
24.576
18.432
36.864
(1)
49.152
(1)
73.728
(2)
—
(2)
—
192 kHz
(1)
(2)
2
This system clock rate is not supported in I C fast mode.
This system clock rate is not supported for the given sampling frequency.
t
(SCKH)
H
2.0 V
0.8 V
System Clock (SCK)
L
t
(SCKL)
t
(SCY)
PARAMETERS
MIN
MAX UNITS
t
System clock pulse cycle time
13
ns
ns
ns
(SCY)
t
System clock pulse duration, HIGH
System clock pulse duration, LOW
0.4t
(SCY)
(SCKH)
t
0.4t
(SCY)
(SCKL)
Figure 23. System Clock Input Timing
14
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