PCM1753
PCM1754
PCM1755
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SLES092A – OCTOBER 2003 – REVISED AUGUST 2004
Power-On Reset Functions
The PCM1753/54/55 includes a power-on reset function. Figure 20 shows the operation of this function. With
the system clock active and V > 3 V (typical, 2.2 V to 3.7 V), the power-on reset function is enabled. The
CC
initialization sequence requires 1024 system clocks from the time V > 3 V (typical, 2.2 V to 3.7 V). After the
CC
initialization period, the PCM1753/55 is set to its reset default state, as described in the Mode Control Registers
section of this data sheet.
During the reset period (1024 system clocks), the analog output is forced to the bipolar zero level, or V /2.
CC
After the reset period, an internal register is initialized in the next 1/f period and if SCK, BCK, and LRCK are
S
provided continuously, the PCM1753/54/55 provides proper analog output with unit group delay against the
input data.
V
CC
3.7 V (Max)
3.0 V (Typ)
2.2 V (Min)
Reset
Reset Removal
Internal Reset
System Clock
Don’t Care
1024 System Clocks
Figure 20. Power-On Reset Timing
13
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