single-ended mode, the converter’s reference voltage is
always the difference between the VREF and GND pins. In
differential mode, the reference voltage is the difference
between the currently enabled switches. See Tables I and II
and Figures 2 through 4 for more information. The last two
bits (PD1 - PD0) select the power- down mode as shown in
Table V. If both inputs are HIGH, the device is always
powered up. If both inputs are LOW, the device enters a
power-down mode between conversions. When a new con-
version is initiated, the device will resume normal operation
instantly—no delay is needed to allow the device to power
up and the very first conversion will be valid. There are two
power-down modes: one where PENIRQ is disabled and
one where it is enabled.
PD1 PD0 PENIRQ DESCRIPTION
0
0
Enabled Power-down between conversions. When each
conversion is finished, the converter enters a low
power mode. At the start of the next conversion,
the device instantly powers up to full power.
There is no need for additional delays to assure
full operation and the very first conversion is
valid. The Y– switch is on while in power-down.
0
1
0
Disabled Same as mode 00, except PENIRQ is disabled.
The Y– switch is off while in power-down mode.
1
1
Disabled Reserved for future use.
1
Disabled No power-down between conversions, device is
always powered.
TABLE V. Power-Down Selection.
CS
tACQ
DCLK
DIN
1
8
1
8
1
8
SER/
DFR
S
A2 A1 A0 MODE
Idle
PD1 PD0
Acquire
(START)
Conversion
Idle
BUSY
DOUT
(1)
11 10
(MSB)
9
8
7
6
5
4
3
2
1
0
Zero Filled...
(LSB)
X/Y SWITCHES
OFF
OFF
ON
OFF
(SER/DFR HIGH)
(1, 2)
X/Y SWITCHES
ON
OFF
(SER/DFR LOW)
NOTES: (1) Y Drivers are on when X+ is selected input channel (A2 - A0 = 001B), X Drivers are on when Y+ is selected
input channel (A2 - A0 = 101B). Y– will turn on when power-down mode is entered and PD1, PD0 = 00B. (2) Drivers will
remain on if power-down mode is 11B (no power-down) until selected input channel, reference mode, or power-down
mode is changed.
FIGURE 5. Conversion Timing, 24-Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required with Dedicated
Serial Port.
CS
DCLK
1
8
1
8
1
8
1
DIN
BUSY
DOUT
S
S
CONTROL BITS
CONTROL BITS
11 10
9
8
7
6
5
4
3
2
1
0
11 10 9
FIGURE 6. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required with Dedicated
Serial Port.
®
9
ADS7843
BB [ BURR-BROWN CORPORATION ]
