However, since the resistance between Y+ and Y– is fairly
low, the on-resistance of the Y drivers does make a small
difference. Under the situation outlined so far, it would not
be possible to achieve a zero volt input or a full-scale input
regardless of where the pointing device is on the touch
screen because some voltage is lost across the internal
switches. In addition, the internal switch resistance is un-
likely to track the resistance of the touch screen, providing
an additional source of error.
complete conversion can be accomplished with three serial
communications, for a total of 24 clock cycles on the DCLK
input.
The first eight clock cycles are used to provide the control
byte via the DIN pin. When the converter has enough
information about the following conversion to set the input
multiplexer, switches, and reference inputs appropriately,
the converter enters the acquisition (sample) mode and, if
needed, the internal switches are turned on. After three more
clock cycles, the control byte is complete and the converter
enters the conversion mode. At this point, the input sample/
hold goes into the hold mode and the internal switches may
turn off. The next twelve clock cycles accomplish the actual
analog-to-digital conversion. If the conversion is ratiometric
(SER/DFR LOW), the internal switches are on during the
conversion. A thirteenth clock cycle is needed for the last bit
of the conversion result. Three more clock cycles are needed
to complete the last byte (DOUT will be LOW). These will
be ignored by the converter.
This situation can be remedied as shown in Figure 4. By
setting the SER/DFR bit LOW, the +REF and –REF inputs
are connected directly to Y+ and Y–. This makes the analog-
to-digital conversion ratiometric. The result of the conver-
sion is always a percentage of the external resistance, re-
gardless of how it changes in relation to the on-resistance of
the internal switches. Note that there is an important consid-
eration regarding power dissipation when using the
ratiometric mode of operation, see the Power Dissipation
section for more details.
Control Byte
+VCC
Also shown in Figure 5 is the placement and order of the
control bits within the control byte. Tables III and IV give
detailed information about these bits. The first bit, the ‘S’ bit,
must always be HIGH and indicates the start of the control
byte. The ADS7843 will ignore inputs on the DIN pin until
the start bit is detected. The next three bits (A2 - A0) select
the active input channel or channels of the input multiplexer
(see Tables I and II and Figure 2). The MODE bit determines
the number of bits for each conversion, either 12 bits (LOW)
or 8 bits (HIGH).
Y+
+REF
+IN
X+
Converter
–IN
–REF
The SER/DFR bit controls the reference mode: either single-
ended (HIGH) or differential (LOW). (The differential mode
is also referred to as the ratiometric conversion mode.) In
Y–
GND
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(MSB)
(LSB)
FIGURE 4. Simplified Diagram of Differential Reference
(SER/DFR LOW, Y Switches Enabled, X+ is
Analog Input).
S
A2
A1
A0
MODE SER/DFR PD1
PD0
TABLE III. Order of the Control Bits in the Control Byte.
As a final note about the differential reference mode, it must
be used with +VCC as the source of the +REF voltage and
cannot be used with VREF. It is possible to use a high
precision reference on VREF and single-ended reference
mode for measurements which do not need to be ratiometric.
Or, in some cases, it could be possible to power the con-
verter directly from a precision reference. Most references
can provide enough power for the ADS7843, but they might
not be able to supply enough current for the external load
(such as a resistive touch screen).
BIT
NAME
DESCRIPTION
7
S
Start Bit. Control byte starts with first HIGH bit on
DIN. A new control byte can start every 15th clock
cycle in 12-bit conversion mode or every 11th clock
cycle in 8-bit conversion mode.
6 - 4
A2 - A0
MODE
Channel Select Bits. Along with the SER/DFR bit,
these bits control the setting of the multiplexer input,
switches, and reference inputs, as detailed in Tables
I and II.
3
2
12-Bit/8-Bit Conversion Select Bit.This bit controls
the number of bits for the following conversion: 12-
bits (LOW) or 8-bits (HIGH).
SER/DFR Single-Ended/Differential Reference Select Bit. Along
with bits A2 - A0, this bit controls the setting of the
multiplexer input, switches, and reference inputs, as
detailed in Tables I and II.
DIGITAL INTERFACE
Figure 5 shows the typical operation of the ADS7843’s digital
interface. This diagram assumes that the source of the digital
signals is a microcontroller or digital signal processor with a
basic serial interface. Each communication between the pro-
1 - 0 PD1 - PD0 Power-Down Mode Select Bits. See Table V for
details.
TABLE IV. Descriptions of the Control Bits within the
Control Byte.
cessor and the converter consists of eight clock cycles. One
®
ADS7843
8
BB [ BURR-BROWN CORPORATION ]
