16-Clocks per Conversion
programmable gate arrays (FPGAs) or application specific
integrated circuits (ASICs). Note that this effectively in-
creases the maximum conversion rate of the converter be-
yond the values given in the specification tables, which
assume 16 clock cycles per conversion.
The control bits for conversion n+1 can be overlapped with
conversion ‘n’ to allow for a conversion every 16 clock
cycles, as shown in Figure 6. This figure also shows pos-
sible serial communication occurring with other serial pe-
ripherals between each byte transfer between the processor
and the converter. This is possible provided that each
conversion completes within 1.6ms of starting. Otherwise,
the signal that has been captured on the input sample/hold
may droop enough to affect the conversion result. Note that
the ADS7843 is fully powered while other serial communi-
cations are taking place during a conversion.
SYMBOL
tACQ
tDS
DESCRIPTION
MIN
TYP
MAX
UNITS
µs
ns
Acquisition Time
1.5
DIN Valid Prior to DCLK Rising 100
tDH
DIN Hold After DCLK HIGH
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
10
ns
tDO
200
200
200
ns
tDV
ns
tTR
ns
Digital Timing
tCSS
tCSH
tCH
CS Falling to First DCLK Rising 100
ns
CS Rising to DCLK Ignored
DCLK HIGH
0
ns
Figure 7 and Table VI provide detailed timing for the digital
interface of the ADS7843.
200
200
ns
tCL
DCLK LOW
ns
tBD
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
200
200
200
ns
15-Clocks per Conversion
tBDV
tBTR
ns
Figure 8 provides the fastest way to clock the ADS7843.
This method will not work with the serial interface of most
microcontrollers and digital signal processors as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method could be used with field
ns
TABLE VI. Timing Specifications (+VCC = +2.7V and
Above, TA = –40°C to +85°C, CLOAD = 50pF).
CS
tCL
tCSH
tCSS
tCH
tBD
tBD
tD0
DCLK
DIN
tDH
tDS
PD0
tBDV
tBTR
BUSY
DOUT
tDV
tTR
11
10
FIGURE 7. Detailed Timing Diagram.
CS
DCLK
1
15
1
15
1
SGL/
SGL/
DIF
DIN
BUSY
DOUT
S
A2 A1 A0 MODE
PD1 PD0
S
A2 A1 A0 MODE
PD1 PD0
S
A2 A1 A0
DIF
11 10
9
8
7
6
5
4
3
2
1
0
11 10
9
8
7
6
5
4
3
2
FIGURE 8. Maximum Conversion Rate, 15-Clocks per Conversion.
®
ADS7843
10
BB [ BURR-BROWN CORPORATION ]
