ANALOG INPUT
THEORY OF OPERATION
Figure 2 shows a block diagram of the input multiplexer on
the ADS7843, the differential input of the A/D converter, and
the converter’s differential reference. Table I and Table II
show the relationship between the A2, A1, A0, and SER/DFR
control bits and the configuration of the ADS7843. The
control bits are provided serially via the DIN pin—see the
Digital Interface section of this data sheet for more details.
The ADS7843 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a
0.6µs CMOS process.
The basic operation of the ADS7843 is shown in Figure 1.
The device requires an external reference and an external
clock. It operates from a single supply of 2.7V to 5.25V. The
When the converter enters the hold mode, the voltage differ-
ence between the +IN and –IN inputs (see Figure 2) is
captured on the internal capacitor array. The input current on
the analog inputs depends on the conversion rate of the
device. During the sample period, the source must charge the
internal sampling capacitor (typically 25pF). After the ca-
pacitor has been fully charged, there is no further input
current. The rate of charge transfer from the analog source to
the converter is a function of conversion rate.
external reference can be any voltage between 1V and +VCC
.
The value of the reference voltage directly sets the input
range of the converter. The average reference input current
depends on the conversion rate of the ADS7843.
The analog input to the converter is provided via a four-
channel multiplexer. A unique configuration of low on-
resistance switches allows an unselected ADC input channel
to provide power and an accompanying pin to provide ground
for an external device. By maintaining a differenital input to
the converter and a differential reference architecture, it is
possible to negate the switch’s on-resistance error (should
this be a source of error for the particular measurement).
A2
A1
A0
X+
Y+
IN3
IN4
–IN(1)
X SWITCHES
Y SWITCHES
+REF(1)
–REF(1)
0
1
0
1
0
0
1
1
1
1
0
0
+IN
GND
GND
GND
GND
OFF
ON
ON
+VREF
+VREF
+VREF
+VREF
GND
GND
GND
GND
+IN
OFF
OFF
OFF
+IN
OFF
OFF
+IN
NOTE: (1) Internal node, for clarification only—not directly accessible by the user.
TABLE I. Input Configuration, Single-Ended Reference Mode (SER/DFR HIGH).
A2
A1
A0
X+
Y+
IN3
IN4
–IN(1)
X SWITCHES
Y SWITCHES
+REF(1)
–REF(1)
0
1
0
1
0
0
1
1
1
1
0
0
+IN
–Y
–X
OFF
ON
ON
+Y
+X
–Y
–X
+IN
OFF
OFF
OFF
+IN
GND
GND
OFF
OFF
+VREF
+VREF
GND
GND
+IN
NOTE: (1) Internal node, for clarification only—not directly accessible by the user.
TABLE II. Input Configuration, Differential Reference Mode (SER/DFR LOW).
+2.7V to +5V
1µF
to
10µF
(Optional)
ADS7843
DCLK 16
+
0.1µF
Serial/Conversion Clock
Chip Select
1
2
3
4
5
6
7
8
+VCC
X+
CS 15
DIN 14
Serial Data In
Y+
Touch
Screen
Converter Status
Serial Data Out
Pen Interrupt
X–
BUSY 13
DOUT 12
PENIRQ 11
+VCC 10
Y–
GND
IN3
IN4
100kΩ (optional)
Auxiliary Inputs
VREF
9
0.1µF
FIGURE 1. Basic Operation of the ADS7843.
®
ADS7843
6
BB [ BURR-BROWN CORPORATION ]
