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ADS7824UB 参数 Datasheet PDF下载

ADS7824UB图片预览
型号: ADS7824UB
PDF下载: 下载PDF文件 查看货源
内容描述: 4通道,12位采样CMOS A / D转换器 [4 Channel, 12-Bit Sampling CMOS A/D Converter]
分类和应用: 转换器模数转换器光电二极管
文件页数/大小: 16 页 / 346 K
品牌: BB [ BURR-BROWN CORPORATION ]
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CROSSTALK  
minimal requirement for the drive capability on the signal  
conditioning preceding the A/D. Any op amp sufficient for  
the signal in an application will be sufficient to drive the  
ADS7824.  
With a full-scale 1kHz input signal, worst case crosstalk on  
the ADS7824 is better than –95dB. This should be adequate  
for even the most demanding applications. However, if  
crosstalk is a concern, the following items should be kept in  
mind:  
The resistive front end of the ADS7824 also provides a  
guaranteed ±15V overvoltage protection. In most cases, this  
eliminates the need for external over voltage protection  
circuitry.  
The worst case crosstalk is generally from Channel 3 to 2. In  
addition, crosstalk from Channel 3 to any other channel is  
worse than from those channels to Channel 3. The reason for  
this is that channel three is nearer to the reference on the  
ADS7824. This allows two coupling modes: channel-to-  
channel and Channel 3 to the reference. In general, when  
crosstalk is a concern, avoid placing signals with higher  
frequency components on Channel 3.  
INTERMEDIATE LATCHES  
The ADS7824 does have tri-state outputs for the parallel  
port, but intermediate latches should be used if the bus will  
be active during conversions. If the bus is not active during  
conversions, the tri-state outputs can be used to isolate the  
A/D from other peripherals on the same bus.  
If a particular channel should be as immune as possible from  
crosstalk, Channel 0 would be the best channel for the signal  
and Channel 1 should have the signal with the lowest  
frequency content. If two signals are to have as little crosstalk  
as possible, they should be placed on Channel 0 and Channel  
2 with lower frequency, less-sensitive inputs on the other  
channels.  
Intermediate latches are beneficial on any monolithic A/D  
converter. The ADS7824 has an internal LSB size of 610µV.  
Transients from fast switching signals on the parallel port,  
even when the A/D is tri-stated, can be coupled through the  
substrate to the analog circuitry causing degradation of  
converter performance. The effect of this phenomenon will  
be more obvious when using the pin-compatible ADS7825  
or any of the other 16-bit converters in the ADS Family. This  
is due to the smaller LSB size of 38µV.  
SIGNAL CONDITIONING  
The FET switches used for the sample hold on many CMOS  
A/D converters release a significant amount of charge injec-  
tion which can cause the driving op amp to oscillate. The  
amount of charge injection due to the sampling FET switch  
on the ADS7824 is approximately 5-10% of the amount on  
similar ADCs with the charge redistribution DAC (CDAC)  
architecture. There is also a resistive front end which attenu-  
ates any charge which is released. The end result is a  
For an ADS7824 with proper layout, grounding, and bypass-  
ing; the effect should only be a few tenths of an LSB at the  
most. In those cases where this is not true, it is possible for  
the conversion results to exhibit random errors of many  
LSBs. Poor grounding, poor bypassing, and high-speed  
digital signals will increase the magnitude of the errors.  
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ADS7824  
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