STARTING A CONVERSION
The combination of CS (pin 23) and R/C (pin 22) LOW for
a minimum of 40ns places the sample/hold of the ADS7824
in the hold state and starts conversion ‘n’. BUSY (pin 24)
will go LOW and stay LOW until conversion ‘n’ is com-
pleted and the internal output register has been updated. All
new convert commands during BUSY LOW will be ignored.
CS and/or R/C must go HIGH before BUSY goes HIGH or
a new conversion will be initiated without sufficient time to
acquire a new signal.
The ADS7824 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert com-
mands assures accurate acquisition of a new signal. Refer to
Tables Ia and Ib for a summary of CS, R/C, and BUSY states
and Figures 2 through 6 and Table II for timing information.
CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
INPUTS
CS
1
X
0
0
0
R/C
X
0
1
1
1
BYTE
X
X
0
1
X
CONTC
X
X
X
X
X
PWRD
X
X
X
X
X
BUSY
X
X
X
X
↑
D7
Hi-Z
Hi-Z
D11
(MSB)
D3
↑↓
D6
Hi-Z
Hi-Z
D10
D2
↑↓
D5
Hi-Z
Hi-Z
D9
D1
↑↓
OUTPUTS
D4
Hi-Z
Hi-Z
D8
D0
(LSB)
↑↓
D3
Hi-Z
Hi-Z
D7
LOW
↑↓
D2
Hi-Z
Hi-Z
D6
LOW
↑↓
D1
Hi-Z
Hi-Z
D5
LOW
↑↓
D0
Hi-Z
Hi-Z
D4
LOW
↑↓
COMMENTS
initiating a conversion. If, however, it is critical that CS or
R/C initiates conversion ‘n’, be sure the less critical input is
LOW at least 10ns prior to the initiating input. If EXT/INT
(pin 12) is LOW when initiating conversion ‘n’, serial data
from conversion ‘n – 1’ will be output on SDATA (pin 16)
following the start of conversion ‘n’. See Internal Data
Clock in the Reading Data section.
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. This will
have no effect when using the internal data clock in the serial
output mode. However, the parallel output and the serial
output (only when using an external data clock) will be
affected whenever R/C goes HIGH. Refer to the Reading
Data section and Figures 2, 3, 5, and 6.
Results from last
completed conversion.
Results from last
completed conversion.
Data will change at the
end of a conversion.
TABLE Ia. Read Control for Parallel Data (PAR/SER = 5V.)
CS
Input
1
X
0
R/C
Input
X
0
↓
CONTC PWRD
Input
X
X
0
Input
X
X
X
BUSY
Output
1
1
1
D7, D6, D5
D4
D3
LOW
EXT/INT SYNC
Output
Hi-Z
Hi-Z
Hi-Z
Input
LOW
LOW
LOW
Output
LOW
LOW
LOW
D2
DATACLK
I/O
Output
Output
Output
D1
SDATA
Output
Hi-Z
Hi-Z
Output
D0
TAG
Input
X
X
X
COMMENTS
↓
0
0
X
1
Hi-Z
LOW
LOW
Output
Output
X
0
1
0
X
X
Hi-Z
HIGH
LOW
Input
Output
Input
0
1
0
X
↑
Hi-Z
HIGH
LOW
Input
Output
Input
0
↑
0
X
1
Hi-Z
HIGH
LOW
Input
Output
X
↓
1
0
X
1
Hi-Z
HIGH
LOW
Input
Output
X
0
0
1
0
↓
Hi-Z
LOW
LOW
Output
Output
X
↓
0
↓
0
1
↑
0
↓
X
X
1
1
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
HIGH
HIGH
LOW
LOW
Output
Output
LOW
LOW
Input
Input
Output
Output
Output
Output
Output
Output
X
X
X
X
Starts transmission of data from previous
conversion on SDATA synchronized to 12
pulses output on DATACLK.
Starts transmission of data from previous
conversion on SDATA synchronized to 12
pulses output on DATACLK.
The level output on SDATA will be the level
input on TAG 12 DATACLK input cycles
earlier.
At the end of the conversion, when BUSY
rises, data from the conversion will be shifted
into the output registers. If DATACLK is HIGH,
valid data will be lost.
Initiates transmission of a HIGH pulse on
SYNC followed by data from last completed
conversion on SDATA synchronized to the
input on DATACLK.
Initiates transmission of a HIGH pulse on
SYNC followed by data from last completed
conversion on SDATA synchronized to the
input on DATACLK.
Starts transmission of data from previous
conversion on SDATA synchronized to 12
pulses output on DATACLK
SDATA becomes active. Inputs on DATACLK
shift out data.
SDATA becomes active. Inputs on DATACLK
shift out data.
Restarts continuous conversion mode (n – 1 data
transmitted when BUSY is LOW).
Restarts continuous conversion mode (n – 1 data
transmitted when BUSY is LOW).
TABLE Ib. Read Control for Serial Data (PAR/SER = 0V.)
®
ADS7824
8
BURR-BROWN [ BURR-BROWN CORPORATION ]
