rising and falling edges of the internal data clock. The rising
edge of BUSY (pin 24) can be used to latch the data. After
the 12th clock pulse, DATACLK will remain LOW until the
next conversion is initiated, while SDATA will go to what-
ever logic level was input on TAG (pin 17) during the first
clock pulse. The SDATA output will tri-state when BUSY
returns HIGH. Refer to Table II and Figure 4 for timing
information.
14th falling edge and the 15th rising edge of DATACLK; the
second input bit will be valid on the 15th falling edge and the
16th rising edge, etc. With a continuous data clock, TAG
data will be output on DATA until the internal output
registers are updated with the results from the next conver-
sion. Refer to Table II and Figure 5 for timing information.
EXTERNAL DATA CLOCK (During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n – 1’ can be read and will be valid up to 12µs
after the start of conversion ‘n’. Do not attempt to clock out
data from 12µs after the start of conversion ‘n’ until BUSY
(pin 24) rises; this will result in data loss.
EXTERNAL DATA CLOCK
To use an external clock, tie EXT/INT (pin 12) HIGH. The
external clock is not a conversion clock; it can only be used
as a data clock. To enable the output mode of the ADS7824,
CS (pin 23) must be LOW and R/C (pin 22) must be HIGH.
DATACLK must be HIGH for 20% to 70% of the total data
clock period; the clock rate can be between DC and 10MHz.
Serial data from conversion ‘n’ can be output on SDATA
(pin 16) after conversion ‘n’ is completed or during conver-
sion ‘n + 1’.
NOTE: For the best possible performance when using an
external data clock, data should not be clocked out during a
conversion. The switching noise of the asynchronous data
clock can cause digital feedthrough degrading the converter’s
performance. Refer to Table II and Figure 6 for timing
information.
An obvious way to simplify control of the converter is to tie
CS LOW while using R/C to initiate conversions. While this
is perfectly acceptable, there is a possible problem when
using an external data clock. At an indeterminate point from
12µs after the start of conversion ‘n’ until BUSY rises, the
internal logic will shift the results of conversion ‘n’ into the
output register. If CS is LOW, R/C is HIGH and the external
clock is HIGH at this point, data will be lost. So, with CS
LOW, either R/C and/or DATACLK must be LOW during
this period to avoid losing valid data.
TAG FEATURE
TAG (pin 17) inputs serial data synchronized to the external
or internal data clock.
When using an external data clock, the serial bit stream input
on TAG will follow the LSB output on SDATA (pin 16)
until the internal output register is updated with new conver-
sion results. See Table II and Figures 5 and 6.
The logic level input on TAG for the first rising edge of the
internal data clock will be valid on SDATA after all 12 bits
of valid data have been output.
EXTERNAL DATA CLOCK (After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. With CS
LOW (pin 23) and R/C HIGH (pin 22), valid data from
conversion ‘n’ will be output on SDATA (pin 16) synchro-
nized to the external data clock input on DATACLK (pin
15). Between 15 and 35ns following the rising edge of the
first external data clock, the SYNC output pin will go HIGH
for one full data clock period (100ns minimum). The MSB
will be valid between 25 and 55ns after the rising edge of the
second data clock. The LSB will be valid on the 13th falling
edge and the 14th rising edge of the data clock. TAG (pin
17) will input a bit of data for every external clock pulse.
The first bit input on TAG will be valid on SDATA on the
MULTIPLEXER TIMING
The four channel input multiplexer may be addressed manu-
ally or placed in a continuous conversion mode where all
four channels are sequentially addressed.
CONTINUOUS CONVERSION MODE (CONTC= 5V)
To place the ADS7824 in the continuous conversion mode,
CONTC (pin 25) must be tied HIGH. In this mode, acquisi-
tion and conversions will take place continually, cycling
through all four channels as long as CS, R/C and PWRD are
LOW (See Table III). Whichever address was last loaded
CONTC
CS
R/C
BUSY
PWRD
A0 and A1 OPERATION
0
X
X
X
X
Inputs
Initiating conversion n latches in the levels input on A0 and A1 to select the channel for
conversion 'n + 1'.
0
0
0
0
X
0
↓
X
↓
0
1
1
X
0
0
0
1
Inputs
Inputs
Inputs
Inputs
Conversion in process. New convert commands ignored.
Initiates conversion on channel selected at start of previous conversion.
Initiates conversion on channel selected at start of previous conversion.
0
X
X
All analog functions powered down. Conversions in process or initiated will yield
meaningless data.
1
X
X
X
X
Outputs
The end of conversion n (when BUSY rises) increments the internal channel latches and
outputs the channel address for conversion 'n + 1' on A0 and A1.
1
1
1
1
X
0
↓
X
↓
0
1
1
X
0
0
0
1
Outputs
Outputs
Outputs
Outputs
Conversion in process.
Restarts continuous conversion process on next input channel.
Restarts continuous conversion process on next input channel.
0
X
X
All analog functions powered down. Conversions in process or initiated will yield
meaningless data. Resets selected input channel for next conversion to AIN0.
TABLE III. Conversion Control.
®
ADS7824
13
BB [ BURR-BROWN CORPORATION ]
