CDAC. Capacitor values larger than 2.2(F will have little
affect on improving performance.
CALIBRATION
The ADS7824 has no internal provision for correcting the
individual bipolar zero error or full-scale error for each
individual channel. Instead, the bipolar zero error of each
channel is guaranteed to be below a level which is quite
small for a converter with a ±10V input range (slightly more
than ±2 LSBs). In addition, the channel errors should match
each other to within 1 LSB.
The output of the buffer is capable of driving up to 1mA of
current to a DC load. Using an external buffer will allow the
internal reference to be used for larger DC loads and AC
loads. Do not attempt to directly drive an AC load with the
output voltage on CAP. This will cause performance degra-
dation of the converter.
For the full-scale error, the circuit of Figure 9 can be used.
This will allow the reference to be adjusted such that the
full-scale error for any single channel can be set to zero.
Again, the close matching of the channels will ensure that
the full-scale errors on the other channels will be small.
PWRD
PWRD (pin 26) HIGH will power down all of the analog
circuitry including the reference. Data from the previous
conversion will be maintained in the internal registers and
can still be read. With PWRD HIGH, a convert command
yields meaningless data. When PWRD is returned LOW,
adequate time must be provided in order for the capacitors
on REF (pin 7) and CAP (pin 6) to recharge. For 2.2µF
capacitors, a minimum recharge/settling time of 1ms is
recommended before the conversion results should be con-
sidered valid.
AIN2
AIN3
CAP
+5V
+
R1
1MΩ
2.2µF
2.2µF
LAYOUT
POWER
P1
50kΩ
REF
+
AGND2
The ADS7824 uses 90% of its power for the analog cir-
cuitry, and the converter should be considered an analog
component. For optimum performance, tie both power pins
to the same +5V power supply and tie the analog and digital
grounds together.
FIGURE 9. Full Scale Trim.
The +5V power for the converter should be separate from
the +5V used for the system’s digital logic. Connecting VS1
and VS2 (pins 28 and 27) directly to a digital supply can
reduce converter performance due to switching noise from
the digital logic. For best performance, the +5V supply can
be produced from whatever analog supply is used for the rest
of the analog signal conditioning. If +12V or +15V supplies
are present, a simple +5V regulator can be used. Although it
is not suggested, if the digital supply must be used to power
the converter, be sure to properly filter the supply. Either
using a filtered digital supply or a regulated analog supply,
both VS1 and VS2 should be tied to the same +5V source.
REFERENCE
The ADS7824 can operate with its internal 2.5V reference or
an external reference. By applying an external reference to
pin 7, the internal reference can be bypassed.
REF
REF (pin 7) is an input for an external reference or the output
for the internal 2.5V reference. A 2.2µF capacitor should be
connected as close to the REF pin as possible. This capacitor
and the output resistance of REF create a low pass filter to
bandlimit noise on the reference. Using a smaller value
capacitor will introduce more noise to the reference degrad-
ing the SNR and SINAD. The REF pin should not be used
to drive external AC or DC loads.
GROUNDING
Three ground pins are present on the ADS7824. DGND is
the digital supply ground. AGND2 is the analog supply
ground. AGND1 is the ground which all analog signals
internal to the A/D are referenced. AGND1 is more suscep-
tible to current induced voltage drops and must have the path
of least resistance back to the power supply.
The range for the external reference is 2.3V to 2.7V and
determines the actual LSB size. Increasing the reference
voltage will increase the full scale range and the LSB size of
the converter which can improve the SNR.
All the ground pins of the A/D should be tied to an analog
ground plane, separated from the system’s digital logic
ground, to achieve optimum performance. Both analog and
digital ground planes should be tied to the ‘system’ ground
as near to the power supplies as possible. This helps to
prevent dynamic digital ground currents from modulating
the analog ground through a common impedance to power
ground.
CAP
CAP (pin 6) is the output of the internal reference buffer. A
2.2µF capacitor should be placed as close to the CAP pin as
possible to provide optimum switching currents for the
CDAC throughout the conversion cycle. This capacitor also
provides compensation for the output of the buffer. Using a
capacitor any smaller than 1µF can cause the output buffer
to oscillate and may not have sufficient charge for the
®
ADS7824
15
BB [ BURR-BROWN CORPORATION ]
