after the start of conversion ‘n’. Do not attempt to read data
beyond 12µs after the start of conversion ‘n’ until BUSY
(pin 24) goes HIGH; this may result in reading invalid data.
Refer to Table II and Figures 2 and 3 for timing constraints.
READING DATA
PARALLEL OUTPUT
To use the parallel output, tie PAR/SER (pin 20) HIGH. The
parallel output will be active when R/C (pin 22) is HIGH and
CS (pin 23) is LOW. Any other combination of CS and R/C
will tri-state the parallel output. Valid conversion data can be
read in two 8-bit bytes on D7-D0 (pins 9-13 and 15-17). When
BYTE (pin 21) is LOW, the 8 most significant bits will be
valid with the MSB on D7. When BYTE is HIGH, the 4 least
significant bits will be valid with the LSB on D4. BYTE can
be toggled to read both bytes within one conversion cycle.
SERIAL OUTPUT
When PAR/SER (pin 20) is LOW, data can be clocked out
serially with the internal data clock or an external data clock.
When EXT/INT (pin 12) is LOW, DATACLK (pin 15) is an
output and is always active regardless of the state of CS (pin
23) and R/C (pin 22). The SDATA output is active when
BUSY (pin 24) is LOW. Otherwise, it is in a tri-state
condition. When EXT/INT is HIGH, DATACLK is an input.
The SDATA output is active when CS is LOW and R/C is
HIGH. Otherwise, it is in a tri-state condition. Regardless of
the state of EXT/INT, SYNC (pin 13) is an output and always
active, while TAG (pin 17) is always an input.
Upon initial power up, the parallel output will contain
indeterminate data.
PARALLEL OUTPUT (After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. Valid data
from conversion ‘n’ will be available on D7-D0 (pins 9-13
and 15-17). BUSY going HIGH can be used to latch the
data. Refer to Table II and Figures 2 and 3 for timing
constraints.
INTERNAL DATA CLOCK (During A Conversion)
To use the internal data clock, tie EXT/INT (pin 12) LOW.
The combination of R/C (pin 22) and CS (pin 23) LOW will
initiate conversion ‘n’ and activate the internal data clock
(typically 900kHz clock rate). The ADS7824 will output 12
bits of valid data, MSB first, from conversion ‘n – 1’ on
SDATA (pin 16), synchronized to 12 clock pulses output on
DATACLK (pin 15). The data will be valid on both the
PARALLEL OUTPUT (During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n – 1’ can be read and will be valid up to 12µs
SYMBOL
t1
DESCRIPTION
MIN
TYP
MAX
12
UNITS
µs
µs
ns
µs
ns
ns
µs
µs
µs
ns
ns
µs
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Convert Pulse Width
0.04
t2
Start of Conversion to New Data Valid
Start of Conversion to BUSY LOW
BUSY LOW
15
21
t3
85
t4
15
90
40
15
3
21
t5
End of Conversion to BUSY HIGH
Aperture Delay
t6
t7
Conversion Time
21
5
t8
Acquisition Time
t7 + t8
t9
Throughput Time
25
83
Bus Relinquish Time
10
20
12
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
Data Valid to BUSY HIGH
60
15
Start of Conversion to Previous Data Not Valid
Bus Access Time and BYTE Delay
Start of Conversion to DATACLK Delay
DATACLK Period
83
1.4
1.1
75
Data Valid to DATACLK HIGH
DATACLK LOW to Data Not Valid
External DATACLK Period
20
400
100
50
600
External DATACLK HIGH
External DATACLK LOW
40
CS LOW and R/C HIGH to External DATACLK HIGH (Enable Clock)
R/C to CS Setup Time
25
10
CS HIGH or R/C LOW to External DATACLK HIGH (Disable Clock)
DATACLK HIGH to SYNC HIGH
DATACLK HIGH to Valid Data
Start of Conversion to SDATA Active
End of Conversion to SDATA Tri-State
CS LOW and R/C HIGH to SDATA Active
CS HIGH or R/C LOW to SDATA Tri-State
BUSY HIGH to Address Valid
Address Valid to BUSY LOW
25
15
35
55
83
83
83
83
20
25
500
TABLE II. Conversion, Data, and Address Timing. TA = –40°C to +85°C.
®
ADS7824
12
BB [ BURR-BROWN CORPORATION ]
