SPECIFICATIONS
All specifications at TMIN to TMAX, VDD = +5V, CLK = 16MHz, and VREF = 4.096, unless otherwise specified.
ADS1252U
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Input Voltage Range(1)
Input Impedance (differential)
Input Capacitance
0
±VREF
V
R = 6 ÷ (20pF • CLK)
19
20
5
kΩ
pF
pA
nA
Input Leakage
At +25°C
At TMIN to TMAX
50
1
DYNAMIC CHARACTERISTICS
Data Rate
Bandwidth
41.7
kHz
kHz
–3dB
9
Serial Clock (SCLK)
System Clock Input (CLK)
16
16
MHz
MHz
ACCURACY
Integral Linearity Error(2)
THD
Noise
±0.0004
97
2.5
±0.0015
% of FSR
1kHz Input; 0.1dB below FS
dB
ppm of FSR, rms
Bits
3.8
Resolution
24
No Missing Codes
Common-Mode Rejection(3)
Gain Error
Offset Error
Gain Sensitivity to VREF
Power Supply Rejection Ratio
24
100
0.4
±100
1:1
80
Bits
dB
% of FSR
ppm of FSR
at DC
90
60
1
±200
VREF = 4.096V ±0.1V
dB
PERFORMANCE OVER TEMPERATURE
Offset Drift
Gain Drift
0.07
13
ppm/°C
ppm/°C
VOLTAGE REFERENCE
VREF
Load Current
4.096
200
V
µA
DIGITAL INPUT/OUTPUT
Logic Family
CMOS
Logic Level: VIH
+4.0
–0.3
+4.5
+VDD + 0.3
+0.8
V
V
V
V
V
VIL
VOH
VOL
IOH = –500µA
IOL = 500µA
0.4
Input (SCLK, CLK) Histeresis
Data Format
0.6
Offset Two’s Complement
POWER SUPPLY REQUIREMENTS
Operation
Quiescent Current
+4.75
+5
8
+5.25
10
VDC
mA
VDD = +5VDC
Operating Power
Power-Down Current
40
1
50
10
mW
µA
TEMPERATURE RANGE
Operating
Storage
–40
–60
+85
+100
°C
°C
NOTES: (1) In order to achieve the converter’s full-scale range, the input must be fully differential. If the input is single-ended (+VIN or –VIN is fixed), then the
full scale range is one-half that of the differential range. (2) Applies to full-differential signals. (3) The common-mode rejection test is performed with a 100mV
differential input.
®
ADS1252
2
BB [ BURR-BROWN CORPORATION ]
