SLEEP MODE
To force a self-calibration with Sleep Mode, shift 25 bits out
before taking SCLK HIGH to enter Sleep Mode. Self-calibra-
tion will then begin after wakeup. Figure 16 shows the
appropriate timing. Note the extra time needed after wakeup
for calibration before data is ready. The first data after Sleep
Mode with self-calibration is fully-settled and can be used.
Sleep Mode dramatically reduces power consumption (typi-
cally < 1µW with CLK stopped) by shutting down all of the
active circuitry. To enter Sleep Mode, simply hold SCLK
HIGH after DRDY/DOUT goes LOW, as shown in Figure 15.
Sleep Mode can be initiated at any time during read back; it
is not necessary to retrieve all 24 bits of data beforehand.
Once t11 has passed with SCLK held HIGH, Sleep Mode will
activate. DRDY/DOUT stays HIGH once Sleep Mode begins.
SCLK must remain HIGH to stay in Sleep Mode. To exit
Sleep Mode (“wakeup”), set SCLK LOW. The first data after
exiting Sleep Mode is valid. It is not necessary to stop CLK
during Sleep Mode, but doing so will further reduce the digital
supply current.
SINGLE CONVERSIONS
When only single conversions are needed, Sleep Mode can
be used to start and stop the ADS1244. To make a single
conversion, first enter the Sleep Mode holding SCLK HIGH.
Now, when ready to start the conversion, take SCLK LOW.
The ADS1244 will wake up and begin the conversion. Wait
for DRDY/DOUT to go LOW, and then retrieve the data.
Afterwards, take SCLK HIGH to stop the ADS1244 from
converting and re-enter Sleep Mode. Continue to hold SCLK
HIGH until ready to start the next conversion. Operating in
this fashion greatly reduces power consumption since the
ADS1244 is shut down while idle between conversions. Self-
calibrations can be performed prior to the start of the single
conversions by using the waveform shown in Figure 16.
Sleep Mode With Self-Calibration
Self-calibration can be set to run immediately after exiting
Sleep Mode. This is useful when the ADS1244 is put in Sleep
Mode for long periods of time and self-calibration is desired
afterwards to compensate for temperature or supply voltage
changes.
Data ready after wakeup.
Sleep Mode
DRDY/DOUT
SCLK
23
22
21
0
23
Wakeup
1
24
t10
t11
t12
SYMBOL DESCRIPTION
MIN
MAX
UNITS
(1)
t10
SCLK HIGH after DRDY/DOUT goes LOW to activate
Sleep Mode.
0
63.7
ms
(1)
(1)
t11
t12
Sleep Mode activation Time.
66.5
71
66.5
72
ms
ms
Data ready after wakeup.
NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK
period.
FIGURE 15. Sleep Mode Timing; Can be Used for Single Conversions.
Data ready after wakeup and cal.
23
Sleep Mode
DRDY/DOUT
SCLK
23
22
21
0
Wakeup and begin cal.
1
24
25
t11
t13
SYMBOL DESCRIPTION
MIN
MAX
UNITS
ms
(1)
t13
Data ready after wakeup and calibration.
210
211
NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK
period.
FIGURE 16. Sleep Mode with Self-Calibration on Wakeup Timing; Can be Used for Single Conversions.
ADS1244
13
SBAS273
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