SELF-CALIBRATION
When the calibration is complete, DRDY/DOUT will go LOW
indicating that new data is ready. There is no need to alter the
analog input signal applied to the ADS1244 during calibration,
the inputs pins are disconnected within the A/D converter and
the appropriate signals applied internally automatically. The
first conversion after a calibration is fully settled and valid for
use. The time required for a calibration depends on two
independent signals: the falling edge of SCLK and an internal
clock derived from CLK. Variations in the internal calibration
values will change the time required for calibration (t9) within
the range given by the MIN/MAX specs. t12 and t13 described
in the next section are affected likewise.
The user can initiate self-calibration at any time, though in
many applications the ADS1244’s drift performance is good
enough that the self-calibration performing automatically at
power-up is all that is needed. To initiate a self-calibration,
apply at least two additional SCLKs after retrieving 24 bits of
data. Figure 14 shows the timing pattern. The 25th SCLK will
send DRDY/DOUT HIGH. The falling edge of the 26th SCLK
will begin the calibration cycle. Additional SCLK pulses may
be sent after the 26th SCLK, but try to minimize activity on
SCLK during calibration for best results.
Data ready after cal.
DRDY/DOUT
SCLK
23
22
21
0
23
Cal begins.
26
1
24
25
t9
SYMBOL DESCRIPTION
MIN
209
MAX
UNITS
(1)
t9
First data ready after calibration.
210
ms
NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK
period.
FIGURE 14. Self-Calibration Timing.
ADS1244
12
SBAS273
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