DATA RETRIEVAL
retrieval during the update period. DRDY/DOUT will remain
at the state of the last bit shifted out until it is taken HIGH (see
t7), indicating that new data is being updated.
The ADS1244 continuously converts the analog input signal.
To retrieve data, wait until DRDY/DOUT goes LOW, as
shown in Figure 12. After this occurs, begin shifting out the
data by applying SCLKs. Data is shifted out Most Significant
Bit (MSB) first. It is not required to shift out all the 24 bits of
data, but the data must be retrieved before the new data is
updated (see t3) or else it will be overwritten. Avoid data
To avoid having DRDY/DOUT remain in the state of the last
bit, shift a 25th SCLK to force DRDY/DOUT HIGH, see
Figure 13. This technique is useful when a host controlling
the ADS1244 is polling DRDY/DOUT to determine when
data is ready.
Data
Data is ready.
MSB
New data is ready.
LSB
0
DRDY/DOUT
23
22
21
t5
t6
t3
t4
t7
1
24
SCLK
t4
t8
SYMBOL DESCRIPTION
MIN
MAX
UNITS
t3
t4
DRDY/DOUT LOW to first SCLK rising edge.
SCLK positive or negative pulse width.
0
ns
ns
ns
100
50
(1)
t5
SCLK rising edge to new data bit valid:
propagation delay.
t6
SCLK rising edge to old data bit valid: hold time.
Data updating, no read back allowed.
Conversion time (1/data rate).
0
ns
µs
(2)
t7
t8
152
152
(2)
66.667
66.667
ms
NOTES: (1) Load on DRDY/DOUT = 20pF || 100kΩ. (2) Values given for fCLK = 2.4576MHz. For different
CLK frequencies, scale proportional to CLK period. For example, for fCLK = 4.9152MHz, t8 → 33.333ms.
FIGURE 12. Data Retrieval Timing.
Data
Data is ready.
New data is ready.
DRDY/DOUT
SCLK
23
22
21
0
1
24
25
25th SCLK to force DRDY/DOUT HIGH.
FIGURE 13. Data Retrieval with DRDY/DOUT Forced HIGH Afterwards.
ADS1244
11
SBAS273
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