POWER-UP
duces an output code of 7FFFFFH and the negative full-scale
input produces an output code of 800000H. The output clips
at these codes for signals exceeding full-scale. Table I
summarizes the ideal output codes for different input signals.
Self-calibration is performed at power-up to minimize offset and
gain errors. In order for the self-calibration at power-up to work
properly, make sure that both AVDD and DVDD increase
monotonically and are settled by t1, as shown in Figure 11.
SCLK must be held LOW during this time. Once calibration is
complete, DRDY/DOUT will go LOW indicating data is ready
for retrieval. The time required before the first data is ready (t6)
depends on how fast AVDD and DVDD ramp to their final value
(t1). For most ramp rates, t1 + t2 ≈ 350ms (fCLK = 2.4576MHz).
If the system environment is not stable during power-up (the
temperature is varying or the supply voltages are moving
around), it is recommended that a self-calibration be issued
after everything is stable.
INPUT SIGNAL VIN (AINP – AINN)
IDEAL OUTPUT CODE(1)
≥ +2VREF
+2VREF
223 − 1
0
7FFFFFH
000001H
000000H
−2VREF
223 − 1
FFFFFFH
223
223 − 1
≤ − 2VREF
800000H
NOTE: (1) Excludes effects of noise, INL, offset, and gain errors.
DATA FORMAT
TABLE I. Ideal Output Code versus Input Signal.
The ADS1244 outputs 24 bits of data in Binary Two’s
Complement format. The Least Significant Bit (LSB) has a
weight of (2VREF)/(223 – 1). A positive full-scale input pro-
AVDD and DVDD
DRDY/DOUT
Data ready after power-up calibration.
SCLK
t1
t2
SYMBOL DESCRIPTION
MIN
MAX
UNITS
(1)
t1
t2
AVDD and DVDD settling time.
Wait time for calibration and first data conversion.
100
ms
ms
(1)
316
NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional
to CLK period.
FIGURE 11. Power-Up Timing.
ADS1244
10
SBAS273
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