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ADS1224IPWT 参数 Datasheet PDF下载

ADS1224IPWT图片预览
型号: ADS1224IPWT
PDF下载: 下载PDF文件 查看货源
内容描述: 24位模拟数字转换器具有4通道差分输入多路复用器 [24-Bit Analog-to-Digital Converter with 4-Channel Differential Input Multiplexer]
分类和应用: 转换器复用器光电二极管
文件页数/大小: 23 页 / 262 K
品牌: BB [ BURR-BROWN CORPORATION ]
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ꢇ ꢍꢚ ꢛꢀ ꢀꢁ  
www.ti.com  
SBAS286A − JUNE 2003 − REVISED MARCH 2004  
SELF-CALIBRATION  
STANDBY MODE  
Self-calibration can be initiated at any time, although in  
many applications the ADS1224 drift performance is so  
good that the self-calibration performed automatically  
at power-up is all that is needed. To initiate  
self-calibration, apply at least two additional SCLKs  
after retrieving 24 bits of data. Figure 27 shows the  
timing pattern. The 25th SCLK will send DRDY/DOUT  
high. The falling edge of the 26th SCLK will begin the  
calibration cycle. Additional SCLK pulses may be sent  
after the 26th SCLK; however, activity on SCLK should  
be minimized during calibration for best results.  
Standby  
mode  
dramatically  
reduces  
power  
consumption (typically < 1µW with CLK stopped) by  
shutting down all of the active circuitry. To enter Standby  
mode, simply hold SCLK high after DRDY/DOUT goes  
low, as shown in Figure 28. Standby mode can be  
initiated at any time during readback; it is not necessary  
to retrieve all 24 bits of data beforehand.  
When t has passed with SCLK held high, Standby mode  
11  
will activate. DRDY/DOUT stays high when Standby  
mode begins. SCLK must remain high to stay in Standby  
mode. To exit Standby mode (wakeup), set SCLK low.  
The first data after exiting Standby mode is valid. It is not  
necessary to stop CLK during Standby mode, but doing  
so will further reduce the digital supply current.  
When the calibration is complete, DRDY/DOUT goes  
low, indicating that new data is ready. There is no need  
to alter the analog input signal applied to the ADS1224  
during calibration; the input pins are disconnected  
within the A/D converter and the appropriate signals are  
applied internally and automatically. The first  
conversion after a calibration is fully settled and valid for  
use. The time required for a calibration depends on two  
independent signals: the falling edge of SCLK and an  
internal clock derived from CLK. Variations in the  
internal calibration values will change the time required  
Standby Mode With Self-Calibration  
Self-calibration can be set to run immediately after  
exiting Standby mode. This is useful when the  
ADS1224 is put in Standby mode for long periods of  
time and self-calibration is desired afterwards to  
compensate for temperature or supply voltage  
changes.  
for calibration (t ) within the range given by the min/max  
8
To force a self-calibration with Standby mode, shift 25  
bits out before taking SCLK high to enter Standby  
mode. Self-calibration then begins after wakeup.  
Figure 29 shows the appropriate timing. Note the extra  
time needed after wakeup for calibration before data is  
ready. The first data after Standby mode with  
self-calibration is fully settled and can be used.  
specs. t and t described in the next section are  
11  
12  
affected likewise.  
Data Ready After Calibration  
DRDY/DOUT  
SCLK  
23  
22  
21  
0
23  
Calibration Begins  
1
24  
25  
26  
t8  
SYMBOL DESCRIPTION  
(1)  
MIN  
MAX  
UNITS  
t
8
First data ready after calibration  
77.1  
77.9  
ms  
(1)  
Values given for f = 2MHz. For different f  
frequencies, scale proportional to CLK period.  
CLK CLK  
Figure 27. Self-Calibration Timing  
15  
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