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SBAS286A − JUNE 2003 − REVISED MARCH 2004
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The ADS1224 uses a Sinc digital filter to improve noise
performance. Therefore, in certain instances, large
changes in input will require settling time. For example,
an external multiplexer in front of the ADS1224 can put
large changes in input voltage by simply switching input
channels. Abrupt changes in the input will require three
data cycles to settle. When continuously converting,
four readings may be necessary to settle the data. If the
change in input occurs in the middle of the first conver-
sion, three more full conversions of the fully settled input
will be required to get fully settled data. Discard the first
three readings because they will contain only partially−
settled data. Figure 24 illustrates the settling time for
the ADS1224 in Continuous Conversion mode.
Table 2. Ideal Output Code vs Input Signal
INPUT SIGNAL V
(AINP − AINN)
IN
(1)
IDEAL OUTPUT CODE
7FFFFFh
w +2VREF
+2VREF
223 * 1
000001h
000000h
FFFFFFh
0
−2VREF
223 * 1
223
800000h
ǒ
Ǔ
v −2VREF
223 * 1
(1)
Excludes effects of noise, INL, offset, and gain errors.
DATA RETRIEVAL
If the input is known to change abruptly, the mux can be
quickly switched to an alternate channel and quickly
switched back to the original channel. By toggling the
mux, the ADS1224 resets the digital filter and initiates a
new conversion. During this time, the DRDY/DOUT line
is held high until fully-settled data is available.
The ADS1224 continuously converts the analog input
signal. To retrieve data, wait until DRDY/DOUT goes
low, as shown in Figure 25. After this occurs, begin
shifting out the data by applying SCLKs. Data is shifted
out MSB first. It is not required to shift out all 24 bits of
data, but the data must be retrieved before the new data
DATA FORMAT
is updated (see t ) or else it will be overwritten. Avoid
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data retrieval during the update period. DRDY/DOUT
remain at the state of the last bit shifted out until it is
The ADS1224 outputs 24 bits of data in binary two’s
complement format. The least significant bit (LSB) has
a weight of (2VREF)/(2 – 1). The positive full-scale
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taken high (see t ), indicating that new data is being
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updated. To avoid having DRDY/DOUT remain in the
state of the last bit, shift a 25th SCLK to force
DRDY/DOUT high (see Figure 26). This technique is
useful when a host controlling the ADS1224 is polling
DRDY/DOUT to determine when data is ready.
input produces an output code of 7FFFFFh and the
negative full-scale input produces an output code of
800000h. The output clips at these codes for signals
exceeding full-scale. Table 2 summarizes the ideal
output codes for different input signals.
Abrupt change in external VIN
VIN
Second Conversion; Third Conversion;
First Conversion;
Start of
VIN settled, but
digital filter
unsettled
VIN settled, but
digital filter
unsettled
Fourth Conversion;
VIN and digital filter
both settled
includes
conversion
unsettled VIN
DRDY/DOUT
Conversion
time
Figure 24. Settling Time in Continuous Conversion Mode
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