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SBAS286A − JUNE 2003 − REVISED MARCH 2004
To help see the response at lower frequencies,
Figure 21 illustrates the response out to 1kHz. Notice
that signals at multiples of 120Hz are rejected. The
ADS1224 data rate and frequency response scale
0
20
40
60
80
−
−
−
−
directly with CLK frequency. For example, if f
CLK
increases from 2MHz to 4MHz, the data rate increases
from 120SPS to 240SPS, while the notches increase
from 120Hz to 240Hz.
0
−
100
30
40
50
60
70
80
−
−
−
−
20
40
60
80
Input Frequency (Hz)
Figure 22. Frequency Response Near 50Hz and
60Hz with f = 910kHz
CLK
SETTLING TIME
After changing the input multiplexer, selecting the input
buffer, or using temperature sensor, the first data is fully
settled. In the ADS1224, the digital filter is allowed to
settle after toggling any of the MUX0, MUX1, BUFEN,
or TEMPEN pins. Toggling of any of these digital pins
will cause the input to switch to the proper channel, start
conversions, and hold the DRDY/DOUT line high until
the digital filter is fully settled. For example, if MUX0
changes from low to high, selecting a different input
channel, DRDY/DOUT immediately goes high and the
conversion process restarts. DRDY/DOUT goes low
when fully settled data is ready for retrieval. There is no
need to discard any data. Figure 23 shows the timing of
the DRDY/DOUT line as the input multiplexer changes.
−
100
0
100 200 300 400 500 600 700 800 900 1k
Input Frequency (Hz)
Figure 21. Frequency Response to 1kHz
Rejecting 50Hz or 60Hz noise is as simple as choosing
the clock frequency. If simultaneous rejection of 50Hz
and 60Hz noise is desired, f
chosen. The data rate becomes 54.7sps and the
frequency response of the ADS1224 rejects the 50Hz
and 60Hz noise to below 60dB. The frequency
response of the ADS1224 near 50Hz and 60Hz with
= 910kHz can be
CLK
f
= 910kHz is shown in Figure 22.
CLK
MUX0
Abrupt change in internal VIN due to status change (for example, switch channels, temp sensor, buffer enable)
VIN
t1
ADS1224 holds DRDY/DOUT
Fully settled
data ready
until digital filter settles
DRDY/DOUT
DRDY/DOUT suppressed after status change
SYMBOL
(1)
DESCRIPTION
MIN
MAX
UNITS
t
Settling time (DRDY/DOUT held high) after a change in any of the
MUX0, MUX1, BUFEN, or TEMPEN pins
25.9
26.4
ms
1
(1)
Values given for f
CLK
= 2MHz. For different f frequencies, scale proportional to CLK period.
CLK
Figure 23. Example of Settling Time After Changing the Input Multiplexer
12
BB [ BURR-BROWN CORPORATION ]
