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SBAS286A − JUNE 2003 − REVISED MARCH 2004
The falling edges of DRDY/DOUT, indicating that new
data is ready, will vary with respect to each other no
MULTICHANNEL SYSTEMS
Multiple ADS1224s can be operated in parallel to
measure multiple input signals. Figure 31 shows an
example of an eight-channel system. For simplicity, the
supplies and reference circuitry are not shown. The
same CLK signal should be applied to all devices. To
synchronize the ADS1224s, connect the same SCLK
signal to all devices. Then place all the devices in
Standby mode. Afterwards, starting a conversion will
synchronize all the ADS1224s; that is, they will sample
the input signals simultaneously. The DRDY/DOUT
outputs will go low at approximately the same time after
synchronization. When reading data from the devices,
the data appears in parallel on DRDY/DOUT as a result
of the common SCLK connection.
more than time t . This variation is due to possible
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differences in the ADS1224 internal calibration settings.
To account for this, when using multiple devices, either
wait for t to pass after seeing one DRDY/DOUT go
13
low, or wait until all DRDY/DOUTs have gone low before
retrieving data.
Note that changing channels (using the MUX0 and
MUX1 pins), or using the input buffer (BUFEN) or the
temperature sensor (TEMPEN), may require more care
to settle the digital filter. For example, if the MUX0 pin
is toggled on one device and not the other, the
DRDY/DOUT line will be held high until the conversion
settles on the first device. The latter device will continue
conversions through this time. See the Settling Time
section of this datasheet for further details.
ADS1224
AINP1
AINN1
CLK
SCLK
Inputs
AINP4
AINN4
DRDY/DOUT
OUT1
MUX0
MUX1
MUX Select
OUT1
ADS1224
t13
AINP1
AINN1
CLK
SCLK
OUT2
Inputs
AINP4
AINN4
DRDY/DOUT
OUT2
MUX0
MUX1
MUX Select
CLK and SCLK
Sources
SYMBOL
(1)
DESCRIPTION
MIN
MAX
UNITS
t
Difference between DRDY/DOUTs going low in multichannel
systems
0.8
ms
13
(1)
Values given for f
CLK
= 2MHz. For different f frequencies, scale proportional to CLK period.
CLK
Figure 31. Example of Using Multiple ADS1224s in Parallel
18
BB [ BURR-BROWN CORPORATION ]
