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SBAS286A − JUNE 2003 − REVISED MARCH 2004
Data
Data Ready
New Data Ready
MSB
23
LSB
0
DRDY/DOUT
22
21
t4
t5
t2
t3
t6
1
24
SCLK
t3
t7
SYMBOL DESCRIPTION
MIN
MAX UNITS
t
t
DRDY/DOUT low to first SCLK rising edge
SCLK positive or negative pulse width
SCLK rising edge to new data bit valid: propogation delay
SCLK rising edge to old data bit valid: hold time
Data updating; no readback allowed
0
100
ns
ns
ns
ns
µs
ms
2
3
(1)
t
50
4
t
0
48
8.32
5
(1)
(1)
t
t
6
7
Conversion time (1/data rate)
8.32
(1)
Values given for f
CLK
= 2MHz. For different f frequencies, scale proportional to CLK period.
CLK
Figure 25. Data Retrieval Timing
Data
Data Ready
New Data Ready
DRDY/DOUT
SCLK
23
22
21
0
1
24
25
25th SCLK to Force DRDY/DOUT High
Figure 26. Data Retrieval with DRDY/DOUT Forced High Afterwards
14