欢迎访问ic37.com |
会员登录 免费注册
发布采购

ADS1212P 参数 Datasheet PDF下载

ADS1212P图片预览
型号: ADS1212P
PDF下载: 下载PDF文件 查看货源
内容描述: 22位模拟数字转换器 [22-Bit ANALOG-TO-DIGITAL CONVERTER]
分类和应用: 转换器模数转换器光电二极管
文件页数/大小: 41 页 / 807 K
品牌: BB [ BURR-BROWN CORPORATION ]
 浏览型号ADS1212P的Datasheet PDF文件第23页浏览型号ADS1212P的Datasheet PDF文件第24页浏览型号ADS1212P的Datasheet PDF文件第25页浏览型号ADS1212P的Datasheet PDF文件第26页浏览型号ADS1212P的Datasheet PDF文件第28页浏览型号ADS1212P的Datasheet PDF文件第29页浏览型号ADS1212P的Datasheet PDF文件第30页浏览型号ADS1212P的Datasheet PDF文件第31页  
For example, Figure 24 shows that just prior to the DRDY  
signal going LOW, the internal Data Output Register (DOR)  
is updated. This update involves the Offset Calibration  
Register (OCR) and the Full-Scale Register (FSR). If the  
OCR or FSR are being written, their final value may not be  
correct, and the result placed into the DOR will certainly not  
be valid. Problems can also arise if certain bits of the  
Command Register are being changed.  
initiated, the update is blocked. The old output data will  
remain in the DOR and the new data will be lost. The old  
data will remain valid until the read operation has com-  
pleted. In general, multiple instructions may be issued, but  
the last one in any conversion period should be complete  
within 24 • XIN clock periods of the next DRDY LOW  
time. In this usage, “complete” refers to the point where  
DRDY rises in Figures 17 and 19 (in the Timing Section).  
Consult Figures 25 and 26 for the flow of serial data  
during any one conversion period.  
Note that reading the Data Output Register is an excep-  
tion. If the DOR is being read when the internal update is  
Start  
Reading  
ADS1212/13  
drives DRDY LOW  
Start  
Writing  
ADS1212/13  
drives DRDY LOW  
CS  
state  
CS  
state  
HIGH  
HIGH  
LOW  
LOW  
Continuous  
Read  
Mode?  
CS  
state  
Yes  
HIGH  
LOW  
No  
ADS1212/13  
generates 8 serial clock  
cycles and receives  
Instruction Register  
data via SDIO  
ADS1212/13  
generates 8  
serial clock cycles  
and receives  
Instruction Register  
data via SDIO  
ADS1212/13  
generates n  
serial clock cycles  
and receives  
specified  
Use  
SDIO for  
output?  
Yes  
register data  
via SDIO  
No  
SDOUT becomes  
SDIO input to  
active from tri-state  
output transition  
ADS1212/13  
drives DRDY HIGH  
ADS1212/13 generates n  
serial clock cycles  
and transmits specified  
register data via SDOUT  
ADS1212/13 generates n  
serial clock cycles  
and transmits specified  
register data via SDIO  
End  
SDOUT returns to  
tri-state condition  
SDIO transitions to  
tri-state condition  
ADS1212/13  
drives DRDY HIGH  
End  
FIGURE 25. Flowchart for Writing and Reading Register Data, Master Mode.  
27  
®
ADS1212, 1213  
 复制成功!