DRDY
t20
t21
t37
CS
t24
t24
t19
t23
SCLK
IN7
IN7
IN7
IN1
IN1
IN0
INM
IN1
IN0
IN7
SDIO
SDIO
Write Register Data
IN0
OUTM
OUT1 OUT0
IN7
IN7
Read Register Data Using SDIO
IN1 IN0
SDIO
OUTM
Read Register Data Using SDOUT
OUT1 OUT0
SDOUT
DRDY
t16
t20
CS
SCLK
OUTM
Continuous Read of Data Output Register using SDIO
OUTM OUT1 OUT0
Continuous Read of Data Output Register using SDOUT
OUT1 OUT0
SDIO
SDOUT
FIGURE 19. Serial Interface Timing (Using CS), Slave Mode.
t23
t18
t16
DRDY
t21
CS(1)
t26
t25
t17
t22
SCLK
Master
t29
Mode
OUT M
OUT0
t20
IN7
IN6
IN5
IN2
IN1
IN0
IN0
t27
SDIO
SCLK
t24
t26
Slave
Mode
t30
IN7
OUT MSB
OUT0
SDIO
t28
t38
t19
SDIO is an input
SDIO is an output
NOTE: (1) CS is optional.
FIGURE 20. SDIO Input to Output Transition Timing.
t32
t31
DRDY
FIGURE 21. DRDY Rise and Fall Time.
®
25
ADS1212, 1213
BB [ BURR-BROWN CORPORATION ]
