SERIAL INTERFACE
Synchronizing Multiple Converters
A negative going pulse on DSYNC can be used to synchro-
nize multiple ADS1212/13s. This assumes that each
ADS1212 is driven from the same master clock and is set to
the same Decimation Ratio and Turbo Mode Rate. The
affect that this signal has on data output timing in general is
discussed in the Serial Interface section.
The ADS1212/13 includes a flexible serial interface which
can be connected to microcontrollers and digital signal
processors in a variety of ways. Along with this flexibility,
there is also a good deal of complexity. This section de-
scribes the trade-offs between the different types of interfac-
ing methods in a top-down approach—starting with the
overall flow and control of serial data, moving to specific
interface examples, and then providing information on vari-
ous issues related to the serial interface.
The concern here is what happens if the DSYNC input is
completely asynchronous to this master clock. If the DSYNC
input rises at a critical point in relation to the master clock
input, then some ADS1212/13s may start-up one XIN clock
cycle before the others. Thus, the output data will be syn-
chronized, but only to within one XIN clock cycle.
Multiple Instructions
The general timing diagrams which appear throughout this
data sheet show serial communication to and from the
ADS1212/13 occurring during the DRDY LOW period (see
Figures 4 through 10 and Figure 36). This communication
represents one instruction that is executed by the ADS1212/
13, resulting in a single read or write of register data.
For many applications, this will be more than adequate. In
these cases, the timing symbols which relate the DSYNC
signal to the XIN signal can be ignored. For other multiple-
converter applications, this one XIN clock cycle difference
could be a problem. These types of applications would
include using the DRDY and/or the SCLK output from one
ADS1212/13 as the “master” signal for all converters.
However, more than one instruction can be executed by the
ADS1212/13 during any given conversion period (see Fig-
ure 24). Note that DRDY remains HIGH during the subse-
quent instructions. There are several important restrictions
on how and when multiple instructions can be issued during
any one conversion period.
To ensure exact synchronization to the same XIN edge, the
timing relationship between the DSYNC and XIN signals,
as shown in Figure 22, must be observed. Figure 23 shows
a simple circuit which can be used to clock multiple
ADS1212/13s from one ADS1212/13, as well as to ensure
that an asynchronous DSYNC signal will exactly synchro-
nize all the converters.
Internal
Update of DOR
24 • tXIN
DRDY
t34
Serial
I/O
XIN
t35
FIGURE 24. Timing of Data Output Register Update.
t33
DSYNC
The first restriction is that the converter must be in the Slave
Mode. There is no provision for multiple instructions when
the ADS1212/13 is operating in the Master Mode. The
second is that some instructions will produce invalid results
if started at the end of one conversion period and carried into
the start of the next conversion period.
FIGURE 22. DSYNC to XIN Timing for Synchronizing
Mutliple ADS1212/13s.
1/2 74HC74
Asynchronous
DSYNC
Strobe
D
Q
CLK
Q
1/6 74HC04
C1
6pF
DSYNC
XIN
SDOUT
DSYNC
XIN
SDOUT
SDIO
DSYNC
XIN
SDOUT
SDIO
SDIO
SCLK
DVDD
XTAL
XOUT
XOUT
SCLK
DVDD
XOUT
SCLK
DVDD
DGND
DGND
DGND
C2
DGND
6pF
ADS1212/13
ADS1212/13
ADS1212/13
FIGURE 23. Exactly Synchronizing Multiple ADS1212/13s to an Asynchronous DSYNC Signal.
®
26
ADS1212, 1213
BB [ BURR-BROWN CORPORATION ]
