The Command Register (CMR) controls all of the ADS1212/
13’s options and operating modes. These include the PGA
gain setting, the Turbo Mode Rate, the output data rate
(decimation ratio), etc. The CMR is the only 32-bit register
within the ADS1212/13. It, and all the remaining registers,
may be read from or written to.
Each serial communication starts with the 8-bits of the INSR
being sent to the ADS1212/13. This directs the remainder of
the communication cycle, which consists of n bytes being
read from or written to the ADS1212/13. The read/write bit,
the number of bytes n, and the starting register address are
defined, as shown in Table VIII. When the n bytes have been
transferred, the INSR is complete. A new communication
cycle is initiated by sending a new INSR (under restrictions
outlined in the Interfacing section).
Instruction Register (INSR)
The INSR is an 8-bit register which commands the serial
interface either to read or to write “n” bytes beginning at the
specified register location. Table VIII shows the format for
the INSR.
Command Register (CMR)
The CMR controls all of the functionality of the ADS1212/
13. The new configuration takes effect on the negative
transition of SCLK for the last bit in each byte of data being
written to the command register. The organization of the
CMR is shown in Table X.
MSB
LSB
R/W
MB1
MB0
0
A3
A2
A1
A0
TABLE VIII. Instruction Register.
Most Significant Bit
Byte 3
R/W (Read/Write) Bit—For a write operation to occur, this
bit of the INSR must be 0. For a read, this bit must be 1, as
follows:
DSYNC(1)
DRDY
BIAS REFO
DF
U/B
BD
MSB
SDL
0 Off 1 On 0 Two’s 0 Biplr 0 MSByte 0 MSB 0 SDIO
NOTE: (1) DSYNC is Write only, DRDY is Read only.
0
Defaults
R/W
0
1
Write
Read
Byte 2
MD2
MD1
MD0
G2
G1
G0
CH1
CH0
000 Normal Mode
000 Gain 1
00 Channel 1
Defaults
Defaults
Defaults
MB1, MB0 (Multiple Bytes) Bits—These two bits are used
to control the word length (number of bytes) of the read or
write operation, as follows:
Byte 1
SF2
SF1
SF0
DR12 DR11 DR10 DR9 DR8
00000
000 Turbo Mode Rate of 1
MB1
MB0
Byte 0
Least Significant Bit
DR2 DR1 DR0
0
0
1
1
0
1
0
1
1 Byte
2 Bytes
3 Bytes
4 Bytes
DR7
DR6
DR5
DR4
DR3
(00000) 0001 0111 (23) Data Rate of 326Hz
TABLE X. Organization of the Command Register and
Default Status.
A3-A0 (Address) Bits—These four bits select the begin-
ning register location which will be read from or written to,
as shown in Table IX. Each subsequent byte will be read
from or written to the next higher location. (If the BD bit in
the Command Register is set, each subsequent byte will be
read from the next lower location. This bit does not affect the
write operation.) If the next location is not defined in Table
IX, then the results are unknown. Reading or writing contin-
ues until the number of bytes specified by MB1 and MB0
have been transferred.
BIAS (Bias Voltage) Bit—The BIAS bit controls the VBIAS
output state—either on (1.33 • REFIN) or off (disabled), as
follows:
BIAS
VBIAS GENERATOR
VBIAS STATUS
0
1
Off
On
Disabled
1.33•REFIN
Default
The VBIAS circuitry consumes approximately 1mA of steady
state current with no external load. See the VBIAS section for
full details. When the internal reference (REFOUT) is con-
nected to the reference input (REFIN), VBIAS is 3.3V, nominal.
A3
A2
A1
A0
REGISTER BYTE
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
Data Output Register Byte 2 (MSB)
Data Output Register Byte 1
Data Output Register Byte 0 (LSB)
Command Register Byte 3 (MSB)
Command Register Byte 2
REFO (Reference Output) Bit—The REFO bit controls
the internal reference (REFOUT) state, either on (2.5V) or off
(disabled), as follows:
Command Register Byte 1
Command Register Byte 0 (LSB)
Offset Cal Register Byte 2 (MSB)
Offset Cal Register Byte 1
Offset Cal Register Byte 0 (LSB)
Full-Scale Cal Register Byte 2 (MSB)
Full-Scale Cal Register Byte 1
Full-Scale Cal Register Byte 0 (LSB)
REFO
INTERNAL REFERENCE
REFOUT STATUS
0
1
Off
On
High Impedance
2.5V
Default
The internal reference circuitry consumes approximately
1.6mA of steady state current with no external load. See the
Reference Output section for full details on the internal
reference.
Note: MSB = Most Significant Byte, LSB = Least Significant Byte
TABLE IX. A3-A0 Addressing.
®
19
ADS1212, 1213
BB [ BURR-BROWN CORPORATION ]
