R1
3kΩ
A
INP
REFIN
REFOUT
AVDD
±10V
±10V
1.0µF
AIN
N
R2
3kΩ
R3
1kΩ
R4
1kΩ
AGND
AGND
VBIAS
CS
AVDD
MODE
DRDY
SDOUT
SDIO
ADS1212
DVDD
DGND
GND
C1
6pF
DSYNC
XIN
XTAL
XOUT
DGND
SCLK
DVDD
C2
6pF
DVDD
DGND
DGND
FIGURE 12. ±10V Input Configuration Using VBIAS
.
On power-up, external signals may be present before VBIAS
is enabled. This can create a situation in which a negative
voltage is applied to the analog inputs (–2.5V for the circuit
shown in Figure 12), reverse biasing the negative input
protection diode. This situation should not be a problem as
long as the resistors R1 and R2 limit the current being
sourced by each analog input to under 10mA (a potential of
0V at the analog input pin should be used in the calculation).
The circuitry which generates the +2.5V reference can be
disabled via the Command Register and will result in a lower
power dissipation. The reference circuitry consumes a little over
1.6mA of current with no external load. When the ADS1212/13
is in its default state, the internal reference is enabled.
VBIAS
The VBIAS output voltage is dependent on the reference input
(REFIN) voltage and is approximately 1.33 times as great.
This output is used to bias input signals such that bipolar
signals with spans of greater than 5V can be scaled to match
the input range of the ADS1212/13. Figure 12 shows a
connection diagram which will allow the ADS1212/13 to
accept a ±10V input signal (40V full-scale range).
DIGITAL OPERATION
SYSTEM CONFIGURATION
The Micro Controller (MC) consists of an ALU and a
register bank. The MC has two states: power-on reset and
convert. In the power-on reset state, the MC resets all the
registers to their default state, sets up the modulator to a
stable state, and performs self-calibration at a 340Hz data
rate. After this, it enters the Convert Mode, which is the
normal mode of operation for the ADS1212/13.
This method of scaling and offsetting the ±20V differential
input signal will be a concern for those requiring minimum
power dissipation. VBIAS will supply 1.68mA for every chan-
nel connected as shown. For the ADS1213, the current draw
is within the specifications for VBIAS, but, at 12mW, the
power dissipation is significant. If this is a concern, resistors
R1 and R2 can be set to 9kΩ and R3 and R4 to 3kΩ. This will
reduce power dissipation by one-third. In addition, these
resistors can also be set to values which will provide any
arbitrary input range. In all cases, the maximum current into
or out of VBIAS should not exceed its specification of 10mA.
The ADS1212/13 has 5 internal registers, as shown in Table
VII. Two of these, the Instruction Register and the Com-
mand Register, control the operation of the converter. The
Data Output Register (DOR) contains the result from the
most recent conversion. The Offset and Full-Scale Calibra-
tion Registers (OCR and FCR) contain data used for correct-
ing the internal conversion result before it is placed into the
DOR. The data in these two registers may be the result of a
calibration routine, or they may be values which have been
written directly via the serial interface.
Note that the connection diagram shown in Figure 12 causes
a constant amount of current to be sourced by VBIAS. This
will be very important in higher resolution designs as the
voltage at VBIAS will not change with loading, as the load is
constant. However, if the input signal is single-ended and one
side of the input is grounded, the load will not be constant and
VBIAS will change slightly with the input signal. Also, in all
cases, note that noise on VBIAS introduces a common-mode
error signal which is rejected by the converter.
INSR
DOR
CMR
OCR
FCR
Instruction Register
Data Output Register
Command Register
8 Bits
24 Bits
32 Bits
24 Bits
24 Bits
Offset Calibration Register
Full-Scale Calibration Register
TABLE VII. ADS1212/13 Registers.
The circuitry to generate VBIAS is disabled when the
ADS1212/13 is in its default state, and it must be enabled,
via the Command Register, in order for the VBIAS voltage to
be present. When enabled, the VBIAS circuitry consumes
approximately 1mA with no external load.
Communication with the ADS1212/13 is controlled via the
Instruction Register (INSR). Under normal operation, the INSR
is written as the first part of each serial communication. The
instruction that is sent determines what type of communication
will occur next. It is not possible to read the INSR.
®
18
ADS1212, 1213
BB [ BURR-BROWN CORPORATION ]
