Normal operation returns within a single conversion cycle
because it is assumed that the input voltage at the converter’s
input is not removed immediately after the full-scale calibra-
tion is performed. In this case, the digital filter already
contains a valid result.
the input. Conversions proceed as usual over the next three
cycles in order to fill the digital filter. DRDY remains
HIGH during this time. On the next cycle, the DRDY signal
goes LOW indicating valid data and resumption of normal
operation.
For full system calibration, offset calibration must be per-
formed first and then full-scale calibration. The calibration
error will be a sum of the rms noise on the conversion result
and the input signal noise. See the System Calibration Limits
section for information regarding the limits on the magni-
tude of the system full-scale voltage.
The system offset calibration range of the ADS1212/13
is limited and is listed in the Specifications Table. For
more information on how to use these specifications, see
the System Calibration Limits section. To calculate VOS
,
use 2 • REFIN /GAIN for VFS
.
Background Calibration
Pseudo System Calibration
The Background Calibration Mode is entered after the bits
101 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
continuous sequence (see Figure 9). At the start of the next
conversion cycle, the DRDY signal will not go LOW but
will remain HIGH. The inputs to the sampling capacitor are
disconnected from the converter’s analog input and shorted
together. An offset calibration is performed over the next
three conversion periods (in Slave Mode, the very first offset
calibration requires four periods, and all subsequent offset
calibrations require three periods). Then, the input capacitor
is reconnected to the input. Conversions proceed as usual
over the next three cycles in order to fill the digital filter.
DRDY remains HIGH during this time. On the next cycle,
the DRDY signal goes LOW indicating valid data.
The Pseudo System Calibration is performed after the bits
100 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
sequence (see Figure 8). At the start of the next conversion
cycle, the DRDY signal will not go LOW but will remain
HIGH and will continue to remain HIGH throughout the
calibration sequence. The offset calibration will be performed
on the differential input voltage present at the converter’s
input over the next three conversion periods (four in Slave
Mode). Then, the input to the sampling capacitor is discon-
nected from the converter’s analog input and connected
across REFIN. A gain calibration is performed over the next
three conversions.
After this, the Operation Mode bits are reset to 000 (Nor-
mal Mode) and the input capacitor is then reconnected to
Normal
Mode
Pseudo System
Calibration Mode
Normal
Mode
Offset
Calibration on
System Offset(2)
Full-Scale
Calibration on
Internal Full-Scale
Analog
Input
Conversion
Valid
Data
Valid
Data
Valid
Data
Valid
Data
DRDY
PSC(1)
Serial
I/O
tDATA
NOTES: (1) PSC = Pseudo System Calibration instruction. (2) In Slave Mode, this function requires 4 cycles.
FIGURE 8. Pseudo System Calibration Timing.
Normal
Mode
Background Calibration
Mode
Offset
Calibration on
Internal Offset(2)
Analog
Input
Conversion
Full-Scale
Calibration on
Internal Full-Scale
Analog
Input
Conversion
Cycle Repeats
with Offset
Calibration
Valid
Data
Valid
Data
DRDY
BC(1)
Serial
I/O
tDATA
NOTES: (1) BC = Background Calibration instruction. (2) In Slave Mode, the very first offset
calibration will require 4 cycles. All subsequent offset calibrations will require 3 cycles.
FIGURE 9. Background Calibration Timing.
®
15
ADS1212, 1213
BB [ BURR-BROWN CORPORATION ]
