AL462 4K2K Ultra HD FIFO Datasheet
6.2 Pin Description
Write Bus Signals
Pin Name
Ball No
Type Description
DI[31:0]
E16, D17, D16, C17,
C16, B17, A17, A16,
B16, A15, B15, A14,
B14, A13, B13, B12,
B8, A7, B7, A6, B6,
A5,B5, A4, B4, A3,
B3, A2, B2, A1, B1,
C1
I
32/16-bit data inputs; synchronized with the WCLK
clock. Data is acquired at the rising edge of WCLK
clock. The mapping between 32-bit and 16-bit x2
bus configuration are;
DI[7:0]=DIA[7:0]
DI[15:8]=DIA[15:8]
DI[23:16]=DIB[7:0]
DI[31:24]=DIB[15:8]
WEN0 & WEN1
C3, E15
I
I
WEN is the write enable signal that controls the
32/16-bit input data write and write pointer
operation. WEN0 is write enable signal to control all
32-bit bus operation in 32-bit mode (16EN=”L”);
WEN0 and WEN1 are write enable signals to control
dual 16-bit DIA[15:0] and DIB[15:0] bus operation in
16-bit mode (16EN=”H”) respectively.
IE is the data input enable signal that
controls the enabling/ disabling of the
32/16-bit data input pins. The internal write
address pointer is always incremented at the rising
edge of WCLK by enabling WEN regardless of the
IE level. IE0 is data input enable signal to control
all 32-bit bus operation in 32-bit mode (16EN=”L”);
IE0 and IE1 are data input enable signals to
control dual 16-bit DIA[15:0] and DIB[15:0] bus
operation in 16-bit mode
IE0 & IE1
C5, G15
(16EN=”H”) respectively.
A9, F17
I
I
WCLK is the write clock input pin. The write data
input is synchronized with this clock. WCLK0 is
write clock input to control all 32-bit bus
operation in 32-bit mode (16EN=“L”); WCLK0
and WCLK1
are write clock inputs to control dual 16-bit
DIA[15:0] and DIB[15:0] bus operation in
16-bit mode (16EN=“H”) respectively.
The WRST is the write rest signal that resets
the write address pointer to 0. WRST0 is write
rest signal to control all 32-bit bus operation in
32-bit mode (16EN=“L”); WRST0 and WRST1
are write rest signals to control dual 16-bit
DIA[15:0] and DIB[15:0] bus operation in 16-bit
mode (16EN=“H”) respectively.
WCLK0 & WCLK1
C4, F15
WRST0 & WRST1
D15, E14
Write Frame select pin in Two Frame Mode (TFEN
= H):
“L”: Frame 0
WFSEL0 &
WFSEL1
“H”: Frame 1
WFSEL0 is write frame select signal to control all
32-bit bus operation in 32-bit mode (16EN=“L”);
WFSEL0 and WFSEL1
I
are write frame select signals to control dual 16-bit
DIA[15:0] and DIB[15:0] bus operation in 16-bit
mode (16EN=“H”) respectively.
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