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AL462 参数 Datasheet PDF下载

AL462图片预览
型号: AL462
PDF下载: 下载PDF文件 查看货源
内容描述: [Ultra HD FIFO Memory]
分类和应用: 先进先出芯片
文件页数/大小: 38 页 / 3431 K
品牌: AVERLOGIC [ AVERLOGIC TECHNOLOGIES INC ]
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AL462 4K2K Ultra HD FIFO Datasheet  
*Note1: For the polarity definition of all write control signals (WEN, IE and WRST), please refer to the PLRTY  
pin definition and “Memory Operation” section for details.  
Read Bus Signals  
Pin Name  
DO[31:0]  
Ball No  
Type Description  
T16, U15, T15,  
U14, T14, U13,  
T13, U12, T12,  
U11, T11, U10,  
T10, U9, T9, T8,  
T4, U3, T3, U2, T2,  
U1, T1,  
R1, R2, P1, P2, N1,  
N2, M1, M2, L1  
K3, P13  
31/16-bit data outputs; synchronized with the  
O
RCLK clock. Data is output at the rising edge of  
the RCLK clock. The mapping between 32-bit  
and 16-bit x2 bus configuration are;  
DO[7:0]=DOA[7:0]  
DO[15:8]=DOA[15:8]  
DO[23:16]=DOB[7:0]  
DO[31:24]=DOB[15:8]  
REN is the read enable signal that controls the 16-  
bit output data read and read pointer operation.  
REN0 is read enable signal to control all 32-bit bus  
operation in 32-bit mode (16EN=“L”); REN0 and  
REN1 are read enable signals to control dual 16-bit  
DOA[15:0] and DOB[15:0] bus operation  
in 16-bit mode (16EN=“H”) respectively.  
OE is the data input enable signal that controls  
the enabling/ disabling of the 16- bit data output  
pins. The internal read  
REN0 & REN1  
I
I
N4, P15  
OE0 & OE1  
address pointer is always incremented at the rising  
edge of RCLK by enabling REN regardless of the  
OE level. OE0 is data output enable signal to  
control all 32-bit bus operation in 32-bit mode  
(16EN=“L”); OE0 and OE1 are data output enable  
signals to control dual 16-bit DOA[15:0] and  
DOB[15:0] bus operation in 16-bit mode  
(16EN=“H”) respectively.  
U5, U17  
RCLK is the read clock input pin. The read data  
output is synchronized with this clock. RCLK0 is  
read clock output to control all 32-bit bus operation  
in 32-bit mode (16EN=“L”); OCLK0 and WCLK1  
are read clock outputs to control dual 16-bit  
DOA[15:0] and DOB[15:0] bus operation  
in 16-bit mode (16EN=“H”) respectively.  
RCLK0 & RCLK1  
I
U7, R17  
L2, R13  
RCLK loop-out clocks  
RCKO0 & RCKO1  
RENO0 & RENO1  
O
O
RENO0 and RENO1 are “read enable” output  
signals that are synchronous with RCKO0 and  
RCKO1 output clocks respectively  
P8, P11  
L3, P14  
RCKO0 & RCKO1 loop-out clock  
inversion controls;  
RCKOINV0  
&RCKOINV1  
I
I
“L”: RCKO0 & RCKO1 no inversion. “H”: RCKO0 &  
RCKO1 output inverted  
The RRST is the read reset signal that resets the  
read address pointer to 0. RRST0 is read rest  
signal to control all 32-bit bus operation in 32-bit  
mode (16EN=“L”); RRST0 and RRST1 are read  
rest signals to control dual 16-bit DOA[15:0] and  
RRST0 & RRST1  
DOB[15:0] bus operation in 16-bit mode  
©2016~2019 by AverLogic Technologies, Corp.  
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