AL462 4K2K Ultra HD FIFO Datasheet
Miscellaneous Signals
Pin Name
Ball No
Type Description
K1
RSTN
I
I
Global reset (active Low)
Select active polarity of the control signals
C15
PLRTY
including WEN, REN, WRST, RRST, IE, OE,
ROEN and ROINV (total of 8 signals) PLRTY =
VDD33, active low.
PLRTY = GND, active high.
Note: during memory operation, the pin must be
permanently connected to VD33 or GND. If
PLRTY level is changed during memory
operation, memory data is not guaranteed.
F1
XIN
I
Crystal/oscillator input 27 MHz
* Minimum crystal frequency accuracy: ±100 ppm
TMOD2 pin pull-down to enable XIN pin
Crystal output
E1
XOUT
O
N17
VREF1
A
I
Reference voltage input
* Please refer to “External decoupling circuit”
application note for details
L17
M17
D13
VREF2
VSSR1
16EN
A
I
Reference voltage input 2
* Please refer to “External decoupling circuit”
application note for details
Reference voltage ground
-
I
* Please refer to “External decoupling circuit”
application note for details
16-bit bus configuration enable
“L” – 32-bit Input and Output bus width
(Default)
“H” – 16-bit x2 Input and Output bus width
C14
TFEN
I
Two frame mode enable:
“L” – Standard FIFO Mode
“H” – Two Frame Mode
G4
TEST
I
I
I
I
I
I
-
Test pin (pull-down for normal operation, internal
floating)
Test pin (pull-down for normal operation, internal
floating)
Test pin (pull-down for normal operation, internal
floating)
Test PIN (Pull-down crystal/oscillator input from
XIN pin, internal floating)
NC for normal operation (internal pull-down by
default), add 10K ohm pull up circuit for option
NC for normal operation (internal pull-down by
default), add 10K ohm pull up circuit for option
No connect
E3
TMOD0
E4
TMOD1
F4
TMOD2
D10, C9, D9
C8,D8,C7,D7,C6,D6
DLL_CFG[2:0]
DRAM_CFG[5:0]
NC
A11,C2,C12,C13,D3
,D4,D5,D11,D12,D1
4,E5,F3,F5,F14,G5,
G14,H1,H2,H3,H4,H
5,H15,H17,J5,K2,M
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