AL462 4K2K Ultra HD FIFO Datasheet
3 APPLICATIONS
HD video capture and editing systems
Switcher or format converter boxes
Video capture or editing systems
Frame synchronizers
Digital video cameras
Hard disk cache memory
Buffer for communication systems
1080@60p, 4Kx2K@30p video
Video data buffering for security
systems
Scan rate converters
data stream buffering
TBC (Time Base Correction) systems
4 FUNCTION BLOCK DIAGRAM
The internal structure of each AL462 consists of Input/ Output buffers, Write Data
Registers, Read Data Registers and main 16Mx32-bit memory cell array and state-of-the-
art logic design that takes care of addressing and controlling the read/write data.
Input
Buffer
Output
Buffer
512Mbits
Memory Cell
Array
Internal Bus
DO[31:0]
DI[31:0]
32-bit
Internal Bus
32-bit
DRAM Control
WCLK
WRST
IE
RCLK
RRST
OE
Output
Buffer
Control
Input Buffer
Control
Timing Generator
& Arbiter
WEN
REN
WFSEL
RFSEL
To all
Modules
Refresh
Counter
Timing
Generator
XIN
RSTN
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