AL462 4K2K Ultra HD FIFO Datasheet
Read address pointer will be reset to zero and data in
the address 0 is output after RE goes low.
Read address pointer is stopped. Output data is held.
Read address pointer will be reset to zero and output is
high impedance after RE goes low.
L
H
H
H
H
L
L
L
H
Normal Read operation.
Read address pointer increases. Output is high
impedance.
(Data skipping function)
H
H
H
H
L
H
Read address pointer is stopped. Output data is held.
Read operation stopped. Read address pointer is
stopped. Output is high impedance.
PLRTY = GND
RRST REN OE RCLK Function
H
H
H
H
H
L
H
Read reset. The read pointer is reset to zero.
Data in the address 0 is output.
Read reset. The read pointer is reset to zero.
Output is high impedance.
Read address pointer is stopped. Output data is held.
Read address pointer will be reset to zero and data in
the address 0 is output after REN goes low.
Read address pointer is stopped. Output data is held.
Read address pointer will be reset to zero and output is
high impedance after REN goes low.
L
H
H
L
L
L
L
H
H
H
L
Normal Read operation.
Read address pointer increases. Output is high
impedance.
(Data skipping function)
L
L
L
L
H
L
Read address pointer is stopped. Output data is held.
Read operation stopped. Read address pointer is
stopped. Output is high impedance.
9.7 One Field Delay Line (The Old Data Read)
As the design shown in the diagram, by applying the reset every 1-field cycle (with the common signal for
WRST and RRST) and a constant read/write operation (with all WEN, REN, IE and OE tied to active status),
“1 field delay line” timing is shown in the timing chart below. When the difference between the write address
and the read address is 0 (the read address and the write address are the same), the old field data are read
as shown in the timing chart.
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