AL462 4K2K Ultra HD FIFO Datasheet
9.2 FIFO Bus Configurations
FIFO Bus Configurations The FIFO memory can be configured to 32-bit or 16-bit x2 modes and selected by
pin 16EN input pin; where Signal 16EN =
●“0” – 32-bit Input and Output bus width (Default)
●“1” – 16-bit x2 Input and Output bus width.
AL462 32-bit Signal Bus I/O
DO1[15:0] & DO0[15:0] Read Data
DI0[15:0] & DI1[15:0] Write Data
WCLK0, WRST0, WE0 & IE0
32-bit Bus
32-bit Bus
RCLK0, RRST0, RE0 & OE0
FIFO Logic
DRAM
AL462 16-bit x2 Dual Bus I/O
DO0[15:0] Read Data
16-bit Bus
16-bit Bus
DI0[15:0] Write Data
16-bit Bus
16-bit Bus
RCLK0, RRST0,RE0 & OE0
WCLK0, WRST0,WE0 & IE0
DI1[15:0] Write Data
FIFO Logic
DRAM
DO1[15:0] Read Data
RCLK1, RRST1,RE1 & OE1
WCLK1, WRST1,WE1 & IE1
9.3 WRST, RRST Reset Operation
The reset signal can be given at any time regardless of the WEN, REN and OE status. However, they still
need to meet the setup time and hold time requirements with reference to the clock input. When the reset
signal is provided during disabled cycles, the reset operation is not executed until cycles are enabled again.
9.4 Control Signals Polarity Select
The AL462 provides the option for operating polarity on controlling signals. With this feature the application
design can benefit by matching up the operation polarity between the AL462 and an existing interfacing
device without additional glue logic. The operating polarity of control signals WEN, REN, WRST, RRST, IE
and OE are controlled by the PLRTY signal. When PLRTY is pulled high, all 6 signals will be active low.
When PLRTY is pulled low, all 6 signals will be active high.
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