AL462 4K2K Ultra HD FIFO Datasheet
9.5 FIFO Write Operation
In the FIFO write operation, 32 bits of write data are input in synchronization with the WCLK clock. The FIFO
write operation is determined by WRST, WEN, IE and WCLK signals and the combination of these signals
can produce different write results. The PLRTY signal determines the activated polarity of these control
signals. The following tables describe the WRITE functions under different operating polarities.
PLRTY = VDD
WRST WEN
IE WCLK Function
L
-
-
Write reset.
The write pointer is reset to zero.
H
H
L
L
L
H
Normal Write operation.
Write address pointer increases, but no new data will
be written to memory. Old data is retained in memory.
(Write mask function)
H
H
-
Write operation stopped. Write address pointer is also
stopped.
PLRTY = GND
WRST WEN
IE
WCLK Function
H
-
-
Write reset.
The write pointer is reset to zero.
L
L
H
H
H
L
Normal Write operation.
Write address pointer increases, but no new data will
be written to memory. Old data is retained in
memory.
(Write mask function)
L
L
-
Write operation stopped. Write address pointer is
also stopped.
9.6 FIFO Read Operation
In the FIFO read operation, 32 bits of read data are available in synchronization with the RCLK clock. The
access time is stipulated from the rising edge of the RCLK clock. To ensure a valid data read, a minimum of
1.5 Kbyte data write has to occur before any read operations. The FIFO read operation is determined by
RRST, REN, OE and RCLK signals; the combination of these signals could produce varying read results.
The PLRTY signal could decide the activated polarity of these control signals. The following tables describe
the READ functions under different operating polarities.
PLRTY = VDD
RRST REN OE RCLK Function
L
L
L
L
L
H
L
Read reset. The read pointer is reset to zero.
Data in the address 0 is output.
Read reset. The read pointer is reset to zero.
Output is high impedance.
L
H
Read address pointer is stopped. Output data is held.
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