AL462 4K2K Ultra HD FIFO Datasheet
9 FUNCTION DESCRIPTION
9.1 Power-On-Reset & Initialization
During system power-up, a power-on-reset is required for successful initialization of FIFO internal logic. After
deactivation of its reset state, wait for Tdelay_min (2 ms) before applying any operations to ensure the FIFO is in
the normal operating state. Apply a valid reset pulse of WRST and RRST after power-on-reset to guarantee
Read/Write operations start at a known address (address point at zero). The following diagrams illustrate
global reset and R/W reset timings at power-up with polarity equals VDD and GND
Tdelay_min = 2ms
RSTN
XIN
WRST
WCLK
RRST
RCLK
/PLRTY=VDD
Chip Reset& R/W Reset Timing (Power-on-reset)
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