AL462 4K2K Ultra HD FIFO Datasheet
Reset
AL462
WRST RRST
32-bit Input DI[31:0] DO[31:0]
32-bit Output
IE
WEN
OE
REN
WCLK
RCLK
Clock
AL462 1 Field Delay Line Diagram
Field m
Field m + 1
cycle 1
cycle 0
cycle 1
cycle n
cycle 0
RCLK
WCLK
/RRST
/WRST
0
1
n
0
1
DI1[31~0]
tAC
0
1
DO1[31~0]
Data of field m
/PLRTY = VDD
AL462 1 Field Delay Line Timing Diagram
9.8 Two Frame Mode
Two Frame buffering mechanism enables AL462 to store two complete frames simultaneously. This
advantage makes it possible to process two separated frames in parallel for enhancing performance. In
standard FIFO mode, the whole memory space is utilized as single block for sequential data R/W. Once Two
Frame Mode is enabled (TFEN = VDD), AL462 can be configured into two memory blocks. Then the user
can use these two separated blocks independently. While data in one frame is being read, the other can be
written with a new set of data. The desired Read/Write frame is selected via R/W frame select pins WFSEL &
RFSEL. The R/W frame selection and control manipulation are illustrated in the following diagrams.
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