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AS8NVLC512K32QC-20XT 参数 Datasheet PDF下载

AS8NVLC512K32QC-20XT图片预览
型号: AS8NVLC512K32QC-20XT
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×32模块的nvSRAM 3.3V高速SRAM与非易失性存储 [512K x 32 Module nvSRAM 3.3V High Speed SRAM with Non-Volatile Storage]
分类和应用: 存储静态存储器
文件页数/大小: 17 页 / 362 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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SEMICONDUCTOR, INC.  
ADVANCE INFORMATION  
nvSRAM  
AS8nvLC512K32  
Austin Semiconductor, Inc.  
Hardware RECALL (Power Up)  
6. Read Address 0x8FC0 Initiate STORE Cycle  
The software sequence may be clocked with CE controlled reads  
or OE controlled reads. After the sixth address in the sequence is  
entered, the STORE cycle commences and the chip is disabled. HSB  
is driven LOW. It is important to use read cycles and not write cycles  
in the sequence, although it is not necessary that OE be LOW for a  
valid sequence. After the tSTORE cycle time is fulfilled, the SRAM  
is activated again for the read and write operation.  
During power up or after any low power condition (VCC<  
VSWITCH), an internal RECALL request is latched. When VCC  
again exceeds the sense voltage of VSWITCH, a RECALL cycle is  
automatically initiated and takes tHRECALL to complete. During  
this time, HSB is driven LOW by the HSB driver.  
Software STORE  
Transfer data from the SRAM to the nonvolatile memory with a  
software address sequence. The AS8nvLC512K32 software STORE  
cycle is initiated by executing sequential CE controlled read cycles  
from six specific address locations in exact order. During the STORE  
cycle an erase of the previous nonvolatile data is first performed,  
followed by a program of the nonvolatile elements. After a STORE  
cycle is initiated, further input and output are disabled until the  
cycle is completed.  
Software RECALL  
Transfer the data from the nonvolatile memory to the SRAM with  
a software address sequence. A software RECALL cycle is initiated  
with a sequence of read operations in a manner similar to the software  
STORE initiation. To initiate the RECALL cycle, the following  
sequence of CE controlled read operations must be performed.  
1. Read Address 0x4E38 Valid READ  
2. Read Address 0xB1C7 Valid READ  
3. Read Address 0x83E0 Valid READ  
4. Read Address 0x7C1F Valid READ  
5. Read Address 0x703F Valid READ  
6. Read Address 0x4C63 Initiate RECALL Cycle  
Internally, RECALL is a two step procedure. First, the SRAM data  
is cleared; then, the nonvolatile information is transferred into the  
SRAM cells. After the tRECALL cycle time, the SRAM is again  
ready for read and write operations. The RECALL operation does  
not alter the data in the nonvolatile elements.  
Because a sequence of READs from specific addresses is used for  
STORE initiation, it is important that no other read or write accesses  
intervene in the sequence, or the sequence is aborted and no STORE  
or RECALL takes place.  
To initiate the software STORE cycle, the following read  
sequence must be performed.  
1. Read Address 0x4E38 Valid READ  
2. Read Address 0xB1C7 Valid READ  
3. Read Address 0x83E0 Valid READ  
4. Read Address 0x7C1F Valid READ  
5. Read Address 0x703F Valid READ  
Mode Selection  
CE\1Ͳ4  
OE\13  
A15ͲA07  
WE\1Ͳ4  
I/O0Ͳ31  
Mode  
Power  
H
L
X
H
L
X
L
X
X
X
NotSelected  
ReadSRAM  
WriteSRAM  
OutputHighZ  
OutputData  
InputData  
Standby  
Active  
L
X
Active  
Active8  
L
H
L
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x8B45  
ReadSRAM  
ReadSRAM  
ReadSRAM  
ReadSRAM  
ReadSRAM  
AutoStore  
Disable  
OutputData  
OutputData  
OutputData  
OutputData  
OutputData  
OutputData  
Notes  
7. While there are 19 address lines on the AS8nvLC512K32, only the 13 address lines (A14 - A2) are used to control software modes. Rest of the address  
lines are don’t care.  
8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.  
13.WE\ must be HIGH during SRAM read cycles.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS8nvLC512K32  
Rev. 0.0 08/09  
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