AUSTIN SEMICONDUCTOR, INC.
ADVANCE INFORMATION
nvSRAM
AS8nvLC512K32
Austin Semiconductor, Inc.
Hardware RECALL (Power Up)
6. Read Address 0x8FC0 Initiate STORE Cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads. After the sixth address in the sequence is
entered, the STORE cycle commences and the chip is disabled. HSB
is driven LOW. It is important to use read cycles and not write cycles
in the sequence, although it is not necessary that OE be LOW for a
valid sequence. After the tSTORE cycle time is fulfilled, the SRAM
is activated again for the read and write operation.
During power up or after any low power condition (VCC<
VSWITCH), an internal RECALL request is latched. When VCC
again exceeds the sense voltage of VSWITCH, a RECALL cycle is
automatically initiated and takes tHRECALL to complete. During
this time, HSB is driven LOW by the HSB driver.
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a
software address sequence. The AS8nvLC512K32 software STORE
cycle is initiated by executing sequential CE controlled read cycles
from six specific address locations in exact order. During the STORE
cycle an erase of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements. After a STORE
cycle is initiated, further input and output are disabled until the
cycle is completed.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM with
a software address sequence. A software RECALL cycle is initiated
with a sequence of read operations in a manner similar to the software
STORE initiation. To initiate the RECALL cycle, the following
sequence of CE controlled read operations must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation does
not alter the data in the nonvolatile elements.
Because a sequence of READs from specific addresses is used for
STORE initiation, it is important that no other read or write accesses
intervene in the sequence, or the sequence is aborted and no STORE
or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
Mode Selection
CE\1Ͳ4
OE\ꢀ13
A15ͲA0ꢀ7
WE\1Ͳ4
I/O0Ͳ31
Mode
Power
H
L
X
H
L
X
L
X
X
X
NotꢀSelected
ReadꢀSRAM
WriteꢀSRAM
OutputꢀHighꢀZ
OutputꢀData
InputꢀData
Standby
Active
L
X
Active
Activeꢀ8
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
ReadꢀSRAM
ReadꢀSRAM
ReadꢀSRAM
ReadꢀSRAM
ReadꢀSRAM
AutoStore
Disable
OutputꢀData
OutputꢀData
OutputꢀData
OutputꢀData
OutputꢀData
OutputꢀData
Notes
7. While there are 19 address lines on the AS8nvLC512K32, only the 13 address lines (A14 - A2) are used to control software modes. Rest of the address
lines are don’t care.
8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
13.WE\ must be HIGH during SRAM read cycles.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS8nvLC512K32
Rev. 0.0 08/09
4
AUSTIN [ AUSTIN SEMICONDUCTOR ]
