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AS8NVLC512K32QC-20XT 参数 Datasheet PDF下载

AS8NVLC512K32QC-20XT图片预览
型号: AS8NVLC512K32QC-20XT
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×32模块的nvSRAM 3.3V高速SRAM与非易失性存储 [512K x 32 Module nvSRAM 3.3V High Speed SRAM with Non-Volatile Storage]
分类和应用: 存储静态存储器
文件页数/大小: 17 页 / 362 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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SEMICONDUCTOR, INC.  
ADVANCE INFORMATION  
nvSRAM  
AS8nvLC512K32  
Austin Semiconductor, Inc.  
for automatic store operation. Refer to DC Electrical Characteristics  
for the size of VCAP. The voltage on the VCAP pin is driven to VCC  
by a regulator on the chip. Apull up should be placed on WE\ to hold  
it inactive during power up. This pull up is effective only if the WE\  
signal is tri-state during power up. Many MPUs tri-state their  
controls on power up. This should be verified when using the pull  
up. When the nvSRAM comes out of power-on-recall, the MPU  
must be active or the WE\ held inactive until the MPU comes out of  
reset.  
Device Operation  
The AS8nvLC512K32 nvSRAM is made up of two functional  
components paired in the same physical cell. They are  
a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM  
memory cell operates as a standard fast static RAM. Data in the  
SRAM is transferred to the nonvolatile cell (the STORE operation),  
or from the nonvolatile cell to the SRAM (the RECALL operation).  
Using this unique architecture, all cells are stored and recalled in  
parallel. During the STORE and RECALL operations, SRAM read  
and write operations are inhibited. The AS8nvLC512K32 supports  
infinite reads and writes similar to a typical SRAM. In addition, it  
provides infinite RECALL operations from the nonvolatile cells and  
up to 200K STORE operations. See the Truth Table For SRAM  
Operations for a complete description of read and write modes.  
To reduce unnecessary nonvolatile stores, AutoStore and hardware  
store operations are ignored unless at least one write operation has  
taken place since the most recent STORE or RECALL cycle. Software  
initiated STORE cycles are performed regardless of whether a write  
operation has taken place. The HSB\ signal is monitored by the  
system to detect if an AutoStore cycle is in progress.  
SRAM Read  
The AS8nvLC512K32 performs a read cycle when CE\ and OE\ are  
LOW and WE\ and HSB\ are HIGH. The address specified on pins  
A0-18 determines which of the 524,288 data bytes. When the read is  
initiated by an address transition, the outputs are valid after a delay  
of tAA (read cycle 1). If the read is initiated by CE\ or OE\, the outputs  
are valid at tACE or at tDOE, whichever is later (read cycle 2). The data  
output repeatedly responds to address changes within the tAA access  
time without the need for transitions on any control input pins. This  
remains valid until another address change or until CE\ or OE\ is  
brought HIGH, or WE\ or HSB\ is brought LOW.  
Figure 2. AutoStore Mode  
Vcc  
0.1uF  
Vcc  
WE1-4  
VCAP  
VCAP  
VSS  
SRAM Write  
A write cycle is performed when CE\ and WE\ are LOW and HSB\ is  
HIGH. The address inputs must be stable before entering the write  
cycle and must remain stable until CE\ or WE\ goes HIGH at the end  
of the cycle. The data on the common I/O pins DQ0–31 are written  
into the memory if the data is valid tSD before the end of a WE\  
controlled write or before the end of an CE\ controlled write. It is  
recommended that OE\ be kept HIGH during the entire write cycle to  
avoid data bus contention on common I/O lines. If OE\ is left LOW,  
internal circuitry turns off the output buffers tHZWE after WE\ goes  
LOW.  
Hardware STORE Operation  
The AS8nvLC512K32 provides the HSB\6 pin to control and  
acknowledge the STORE operations. Use the HSB\ pin to request a  
hardware STORE cycle. When the HSB pin is driven LOW, the  
AS8nvLC512K32 conditionally initiates a STORE operation after  
t
DELAY.An actual STORE cycle only begins if a write to the SRAM has  
taken place since the last STORE or RECALL cycle. The HSB\ pin  
also acts as an open drain driver that is internally driven LOW to  
indicate a busy condition when the STORE (initiated by any means)  
is in progress.  
AutoStore Operation  
The AS8nvLC512K32 stores data to the nvSRAM using one of the  
following three storage operations: Hardware Store activated by HSB\;  
Software Store activated by an address sequence;AutoStore on device  
power down. The AutoStore operation is a unique feature of  
QuantumTrap technology and is enabled by default on the  
AS8nvLC512K32.  
SRAM read and write operations that are in progress when HSB is  
driven LOW by any means are given time to complete before the  
STORE operation is initiated. After HSB\ goes LOW, the  
AS8nvLC512K32 continues SRAM operations for tDELAY. If a write  
is in progress when HSB\ is pulled LOW it is enabled a time, tDELAY to  
complete. However, any SRAM write cycles requested after HSB\  
goes LOW are inhibited until HSB\ returns HIGH. In case the write  
latch is not set, HSB\ is not driven LOW by the AS8nvLC512K32.  
But any SRAM read and write cycles are inhibited until HSB\ is  
returned HIGH by MPU or other external source.  
During a normal operation, the device draws current from VCC to  
charge a capacitor connected to the VCAP pin. This stored charge is  
used by the chip to perform a single STORE operation. If the voltage  
on the VCC pin drops below VSWITCH, the part automatically disconnects  
the VCAP pin from VCC. A STORE operation is initiated with power  
provided by the VCAP capacitor.  
During any STORE operation, regardless of how it is initiated, the  
AS8nvLC512K32 continues to drive the HSB\ pin LOW, releasing it  
only when the STORE is complete. When the STORE operation is  
completed, the AS8nvLC512K32 remains disabled until the HSB\  
pin returns HIGH. Leave the HSB\ unconnected if it is not used..  
Figure 2 shows the proper connection of the storage capacitor (VCAP  
)
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS8nvLC512K32  
Rev. 0.0 08/09  
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