SDRAM
AS4SD8M16
Austin Semiconductor, Inc.
OPERATION
FIGURE 3: Activating a Specific Row
in a Specific Bank
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to
a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated (see
Figure 3).
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row, subject
to the tRCD specification. tRCD (MIN) should be divided by the
clock period and rounded up to the next whole number to
determine the earliest clock edge after the ACTIVE command
on which a READ or WRITE command can be entered. For
example, a tRCD specification of 20ns with a 125 MHz clock
(8ns period) results in 2.5 clocks, rounded to 3. This is re-
flected in Figure 4, which covers any case where 2 < tRCD
(MIN)/
tCK < 3. (The same procedure is used to convert
other specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active row has
been “closed” (precharged). The minimum time interval
between successive ACTIVE commands to the same bank is
defined by tRC
.
A subsequent ACTIVE command to another bank can be
issued while the first bank is being accessed, which results in a
reduction of total row-access overhead. The minimum time
interval between successive ACTIVE commands to different
banks is defined by tRRD
.
FIGURE 4: Example - Meeting tRCD (MIN) When 2 < tRCD (MIN)/ tCK < 3
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4SD8M16
Rev. 0.5 04/05
9
AUSTIN [ AUSTIN SEMICONDUCTOR ]
